SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

J Deng,Ardasheir Rahman,R Thoma,P Schneider,J D Johnson,Henry Trombley,Ning Lu,Richard Q Williams,Hasan M Nayfeh, Kai Zhao,Russ Robison,Ximeng Guan,N Zamdmer,Steve Shuma,Brian A Worth, James Sundquist,Eric A Foreman,Scott K Springer,R A Wachnik

Electron Devices, IEEE Transactions（2015）

引用 7|浏览78

暂无评分

摘要

In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.

查看译文

关键词

cmos digital integrated circuits,mosfet,monte carlo methods,electronic design automation,flip-flops,nanoelectronics,semiconductor device models,silicon-on-insulator,statistical analysis,timing circuits,fin geometrical variation,monte carlo simulation,soi finfet technology,si,computer-aided design-based statistical modeling,guard time design,latch circuits,latch timing,n-to-p tracking characteristics,nfet-to-pfet tracking variability compact modeling,planar soi high-k metal gate cmos technologies,silicon-on-insulator finfet technology,size 14 nm,integrated circuits design,mosfets,semiconductor device modeling,variation aware timing,variation aware timing.,threshold voltage,logic gates,correlation,doping,silicon on insulator

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要