We developed a spot size converter (SSC) that can be fabricated with a 0.18 µm CMOS process. The SSC has a partial half-height SiN sturucture to reduce polarization dependent loss (PDL). In order to expand the mode field diameter (MFD) and suppress radiation, SiON structures are introduced. As a result of the measurement, the optical losses for mode expansion were 0.5 dB for the transverse electric (TE) mode and 0.7 dB for the transverse magnetic (TM) mode, respectively. PDL was 0.2 dB and the MFD was between 6.0 µmand 8.0 µm.
A novel packaging structure for high-speed and high-density optical transceiver module sufficient for co-packaged optics is proposed. The optical transceiver module consists of a bottom-emitting 16-channel VCSEL array, a back-illuminated 16-channel PD array, a driver array, and TIA array. A multi-core fiber is used for each optical interface of optical transmitter and receiver, and a high-density LGA of 0.3 mm pitch is used for the electrical interface. In order to achieve high-speed and high-density CPO transceiver module, a core-less build-up multi-layer substrate manufactured by modified semi-additive process is used as an interposer. Low loss and low crosstalk characteristics up to several tens of GHz of fine pitch wirings enable to accommodate 25-Gbps× 16-channel optical transceiver in a 7.8 × 10 mm interposer.
In recent years, the development of wide bandgap (WBG) power semiconductors such as SiC and GaN has been gaining momentum. Power-Overlay-kiro-Watt (POL-kW) is an innovative packaging technology that can maximize the electrical and thermal performance of power modules using these WBG power devices. The electrical and thermal properties of POL-kW and the existing structure were verified by simulation and actual measurements. Compared to the existing structure, POL-kW showed up to 58% lower inductance and 8.5% lower cumulative thermal resistance. In addition, for electrical characteristics, high correlation between simulation and actual measurement was obtained on POL-kW compared to the existing structure.
Implementation of next generation 2.5/3D technology for heterogeneous integration requires accurate physical models for signal and power integrity design. We demonstrate a Sum-of-Squares (SOS) partial fraction passivity enforcement algorithm using simulated heterogeneous interconnect data.
Hexagonal-BN (h-BN) based Silicon on Insulator(SOI) structure with Through Silicon Via (TSV) shows higher heat dissipation performance without degradation electrical characteristics compared with the conventional SOI structure. The electrical characteristics and the results are not clear. It is important to clarify the electrical characteristics of h-BN to implement 3D-power Supply on Chip(SoC). This paper investigates electrical characterization of h-BN.
