Hardware Trojans (HTs) have been generally inserted at the lower levels of the digital system design and fabrication process, where, due to the high complexity of the hardware model, their detection is more difficult. However, RTL models are becoming more and more complex, making difficult the identification of malicious behaviours also at this level. Unfortunately, only a few verification techniques have been proposed for the identification of HTs in RTL descriptions. To fill in the gap, this paper proposes a technique that exploits graph-based features and a probabilistic neural network to identify and classify HTs at RTL. The approach identifies suspicious locations inside the RTL description according to a set of known HTs. In addition, it returns a couple of similarity indexes to measure the probability that a suspicious location actually contains a malicious behaviour.
Here we consider one special situation for approximate computing. Given a specification, S, in a truth table and its corresponding multi-level logic circuit implementation, I, S is changed to S' by only changing the truth table value for exactly one minterm from 0 to 1 or 1 to 0. We would like to transform I into I' in such a way that I' is equivalent to S' This is a sort of basic operations for approximate logic synthesis, as the functional changes are minimal (only for one minterm). We experimentally show that even if we change functions for all of the gates in the circuit, I, without changing their input signals (their immediate fanins), i.e., no topological changes, the circuit can never become equivalent to S' for all the cases we tried. However, if we allow to change the function of only one gate in the last level of the circuit, I, and allow to change its input signals as well, the circuit becomes equivalent to S' around 13% of the cases in average with in average additional 1.1 inputs to the gate in the last level. We also experimentally show that one minterm changes in truth tables are, comparing with one and two products changes where all minterms inside the products are changed, the most difficult problems to accommodate from the viewpoint of Engineering Change Order (ECO) or logic debugging, when the circuits are implemented as multi-level logic.
Through silicon via (TSV) based 3D integrated circuits (ICs) have become a popular approach to revive Moore's law. However, the reliability of a TSV is an important issue, as a faulty TSV can result in the failure of the entire 3D IC. Most of TSV faults can be detected during the testing process, however, detecting TSV aging faults during the testing process is impossible. Certain mechanisms are required to be deployed to control the reliability of the chip in the presence of aging faults. In this paper we propose some solutions to repair the TSVs suffering from moderate types of delay fault without re-routing through a spare TSV while meeting the specified constraints of the design. Our experimental results indicate the efficiency of our proposed methods in reducing the adverse effects of an aged TSV in terms of delay reduction.
One of the cost-efficient fabrication approaches for connecting layers in three-dimensional integrated circuits (3D ICs) is the use of through-silicon vias (TSVs). However, the large and closely spaced nature of TSVs has made them seriously prone to coupling capacitances between TSVs, increasing the probability of crosstalk faults. To reduce crosstalk faults in 3D ICs, this paper proposes a dynamic numerical-based crosstalk avoidance mechanism called 3D-DyCAC. The 3D-DyCAC mechanism is applied in two phases. In the first phase, a numerical system-based crosstalk avoidance code (CAC) is proposed to reduce the opposite-direction transitions in adjacent TSVs. This numerical-based CAC generates code words with cumulative groups of 1s and 0s to minimize adjacent transitions in arranged N × N meshes of TSVs. The proposed CAC has no ambiguity in representing code words and generates a unique code word for each data word. In the second phase, a triangular window (TW) is introduced to consider overlaps between the cells of TSVs during the arrangement of code words on TSVs. In the TW area, the content of the victim TSV and/or the content of adjacent bit positions can be dynamically inverted based on the content of data words. Evaluation results show that 3D-DyCAC reduces the area occupation, power consumption, and power-delay product of codec by 10%, 24%, and 46%, respectively, in comparison with state-of-the-art mechanism 3DLAT.
Ensuring the correctness of industrial smart displays applications is fundamental given the requisites concerning reliability and safety demanded by their deployment in industrial plants. However, verification of Human-Machine Interaction applications usually requires an operator using them. This paper presents an approach to automatically verify a set of properties on HMI applications for industrial smart displays. The methodology relies both on static and simulation-based phases to maximize the number of properties automatically verified. The approach has been applied to verify a set of HMI applications developed by an Industrial Smart Display provider.
