In this paper, we present a wideband high-gain low-noise amplifier (LNA) with dual transformer feedback and current-reuse techniques. The first and second stages utilize a current-reuse technique to minimize low power consumption, while the third stage employs a cascode structure for high gain. Dual transformer feedback is applied to the first and second stages to suppress high-frequency gain roll-off, thereby extending the bandwidth. This paper proposes an improved transformer structure, which achieves compact footprint and higher coupling coefficient compared to traditional coupled-line implementations. The proposed wideband LNA is fabricated in 0.15-μm GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process. The measured results show that the proposed LNA achieves a gain of 25.1 dB with a 3-dB bandwidth of 8-19 GHz. The LNA exhibits output 1 dB compression point (OP1dB) of 9 dBm, a minimum noise figure of 1.56 dB, and an S11 value of less than -10 dB across the entire operating bandwidth. The fabricated LNA consumes 84 mW and occupies a chip area of 1.13 mm2 including test pads.
Addressing the critical need for polar decoders that can deliver both high throughput and superior error performance, Belief Propagation with Flipping (BPF) has been studied as an effective scheme. However, the extensive number of processing units (PEs) in traditional BPF decoders results in significant circuit area. To overcome the limitation, this work proposes a Sensitivity-Aware Look-Up Table (LUT)-based Belief Propagation with Flipping (SAL-BPF) decoder, where complex arithmetic functions are replaced by LUTs with message sensitivity analysis. This approach greatly reduces computational complexity and memory access with negligible frame error rate (FER) performance degradation. The proposed SAL-BPF polar decoder with 1024 bit length and 1/2 rate is Synthesized with 28nm CMOS technology. It shows that the proposed LUT-based processing element (PE) achieves over 44% area reduction and 17% delay savings compared with conventional arithmetic PE, with less than 0.35 dB FER performance degradation. The proposed SAL-BPF polar decoder with 6-bit quantization, achieving 1.33 GHz maximum frequency and 0.508 mm2 area. It achieves an excellent trade-off between decoding performance and hardware efficiency.
Time-domain computing-in-memory (CIM) has gained widespread attention in the acceleration of neural network due to its high energy efficiency and large signal margin. However, conventional time-domain CIM architectures face several limitations, including inefficient utilization of sparsity as well as accuracy degradation caused by PVT (process, voltage, temperature) variations, and the high energy and delay overhead of shift-and-add circuits. To address these issues, this work presents a time-domain CIM macro featuring: (1) a zero-weight skipping delay-chain structure that reduce MAC energy and delay by 88.2% and 82.5%, respectively; (2) a self-calibration circuit that reduces offset by 95%; and (3) a shift-and-add embedded time-to-digital converter (TDC) that lowers macro energy consumption and latency by 22.3% and 16.4%, respectively. Evaluation based on the implemented macro shows that when executing VGG16, ResNet-18, and GoogLeNet, the proposed design improves energy efficiency by factors of 1.68×, 2.86×, and 3.18×, and reduces latency by 63.3%, 82.9%, and 91.8%, respectively.
Combinatorial Optimization Problems (COPs) are prevalent across many fields and are mostly NP-hard, posing significant challenges for conventional von Neumann architectures. Ising machines offer a promising alternative by mapping COPs onto spin systems that evolve toward low-energy states. Recent efforts have implemented Ising machines using various technologies, yet silicon-based approaches often suffer from limited parallelism and high energy consumption due to data movement and complex digital sampling. In this paper, we propose a memristor-based Ising machine scheme enhanced by probabilistic neurons that enable analog in-memory annealing. By performing spin updates directly in the analog domain, our architecture eliminates the need for high-precision ADCs and integrates intrinsic stochasticity for efficient exploration of the solution space without extra cost. Our proposed scheme can be easily integrated into existing memristor-based Ising machines and achieves approximately 100% improvement in energy efficiency.
In this work, we investigate the application of Knowledge Distillation (KD) to the Quantum Approximate Optimization Algorithm (QAOA) setting, introducing a framework to distill knowledge from a Multi-angle QAOA teacher to a standard, single-layer QAOA student. We propose three distillation schemes: count-based KD, distillation using MSE, and distillation with Huber loss for enhanced robustness. Numerical experiments on diverse graph families, including complete graphs, Erdős–Rényi graphs, complete binary trees, and random 3-regular graphs, suggest that MSE and Huber-based distillation can improve the student’s performance, while count-based KD exhibits higher variance and limited generalization. Our results indicate that KD can enable a compression of the QAOA parameter space while often maintaining competitive solution quality, providing a practical avenue for efficient deployment on Noisy Intermediate-Scale Quantum hardware with improved training stability.
