Technology Computer-Aided Design (TCAD) is essential for advanced semiconductor device development, enabling the prediction and optimization of device characteristics. As semiconductor devices scale to the nanometer regime with increasing structural complexity, traditional TCAD tools face significant computational bottlenecks when handling large-scale unstructured meshes. To mitigate these efficiency constraints, deep learning-based surrogate models have emerged as a promising approach to accelerate the simulation process. This paper presents a Graph Transformer-based surrogate modeling framework. By combining attention-based aggregation with structural positional encodings, the model enhances topology-aware node representations for TCAD field prediction on unstructured meshes. Validated on the 45-nm MOSFET dataset, the proposed architecture reduces the reliance on training data while maintaining prediction accuracy. Using a dataset comprising 924 total simulation samples, the model attains the R-squared (R2) score of 0.9985 and the Mean Squared Error (MSE) of 3.25 × 10-4. Compared with previous methods, this approach requires less than 50% of the training data typically needed to achieve comparable accuracy. Furthermore, the proposed surrogate model achieves a nearly 694× inference-stage speedup compared with traditional numerical solvers.
This work investigates the effect of externally applied uniaxial mechanical stress (MS) on hot-carrier degradation (HCD) in nMOSFETs. Uniaxial tensile and compressive MS of ±300 MPa are applied via four-point bending to investigate purely mechanical effects. Among the monitored parameters, including threshold voltage shift, saturation current degradation, and linear current degradation, only linear current degradation shows a clear order of tensile > unstressed > compressive. The impact ionization rate and power-law time exponents remain unchanged across the applied MS range, indicating that MS barely alters the trap generation kinetics. The apparent MS separation in linear current degradation is attributed to the MS-dependent initial resistance and the MS-proportional hot-carrier flux. It is also shown that the MS-induced separation decreases at high gate voltage and in devices with shorter and narrower channels. These findings demonstrate that when assessing HCD reliability under MS, the choice of degradation metric, sensing gate voltage, and device geometry must be carefully considered.
Silicon-integrated single-crystal thin-film barium titanate (BaTiO3 or BTO) has recently emerged as a promising material platform for next-generation electro-optic devices due to its exceptionally large electro-optic (Pockels) coefficients. When integrated with Silicon, BTO enables compact, low-voltage, and high-speed devices, which are especially useful in applications that rely on dense meshes of Mach-Zehnder Interferometers (MZIs). However, conventional MZI designs face significant challenges due to the presence of waveguide bends. These introduce bending losses, increase fabrication sensitivity, and limit the overall scalability. In anisotropic materials such as LiNbO3 or BaTiO3, waveguide bends can also cause polarization mixing and unwanted mode coupling, further degrading device performance. In this work, we utilize one of the large electro-optic coefficients of BTO (r33 = 134.4 pm/V) to design an improved MZI architecture that eliminates the need for waveguide bends. Our simulation and analytical results demonstrate a low-frequency (f < 10 MHz) half-wave voltage-length product (Vπ · L) of 0.78 V·cm, with 3-dB modulation bandwidths of 5.50 GHZ and 5.75 GHz for device lengths of 3 mm and 2 mm, respectively. The proposed bend-less structure reduces optical losses, minimizes footprint, and enhances scalability for dense photonic integrated circuits.
This work investigates the root causes of output voltage (VOUT) degradation in a 40V EDPMOS technology used in mobile power-management ICs (PMICs). By combining device electrical characterization, SCM analysis, and process-module experiments, we identify photoresist-induced implant shadowing in the high voltage N-well (HVNW) formation step as a dominant contributor to VOUT loss. A systematic study of photoresist thickness scaling and implant-angle optimization demonstrates that both thinner photoresist and quadro-angle ion implantation independently and significantly improve HVNW doping uniformity, resulting in increased VOUT.
Strain and defect engineering are widely employed to tune the electronic properties of two-dimensional semiconductors. In reality, both stress and defects coexist; however, their coupled impact remains poorly understood. Here, we present a systematic first-principles study of the interplay between mechanical stress and defect functionalization in monolayer WS2. Uniaxial and biaxial stresses (up to ±2 GPa) are applied to pristine, mono-sulfur vacancy, and Halogen-functionalized WS2 monolayers, including iodine substitution and adsorption of iodine/fluorine. Tensile stress results in significantly stronger electronic modulation, with a reduction in bandgap of ∼30%, compared to a ∼7.5% increase under compression. For both uniaxial and biaxial stresses, the doping polarity remains invariant, with substituted iodine exhibiting n-type behavior and adsorbed halogens inducing p-type characteristics. The effective doping strength is strongly stress-dependent, as evidenced by band-edge shifts and charge redistribution. Uniaxial tensile stress enhances donor activation for both halogen-absorbed and substituted WS2. Similarly, for sulfur vacancies, uniaxial tensile stress breaks the symmetry and splits W-d derived defect states, shifting them towards the conduction band and enhancing p-type character. These results reveal stress as an efficient amplifier of defect-induced electronic modulation and establish stress–defect co-engineering as a practical strategy to modulate carrier type, Fermi-level alignment, and transport properties in WS2 for next-generation nanoelectronics applications.
