This paper presents a multiplex coupled magnetics power architecture which extends the bandwidth of arbitrary waveform synthesis beyond the switching frequency. The architecture decouples the switching frequency from the pulse-width-modulation sampling and passive component ripple frequencies using multiphase and multilevel switching cells, allowing it to generate high-power, high-frequency arbitrary waveforms without prohibitively high switching frequencies. Coupled magnetics are used to balance the multilevel voltages, allowing the architecture to synthesize high-frequency signals with low distortion, scale to large multiplexing ratios while maintaining power balancing, and reduce the inductor size, ripple, and loss. The architecture can supply loads with high-power, high-bandwidth arbitrary waveforms, as demonstrated in this paper with an LED driver for visible light communications. A four-phase, seven-level prototype with coupled inductors is used to drive 1,000 W of wide-angle LEDs with 95.8% efficiency while simultaneously transmitting data at 6.4 Mbps over 20 meters.
This paper proposes a high-gain DC-DC converter with single-switch and multi-coupled inductors for renewable energy systems. To obtain high voltage gain, the proposed converter combines a dual-winding coupled inductor and a three-winding coupled inductor (TWCL) to form a charge pump structure with multiple capacitors. At the same time, the required ultra‑high voltage gain can be met by selecting suitable turns ratios of the coupled inductors, instead of forcing the converter to operate at a high duty cycle. The proposed converter has four degrees of freedom to flexibly adjust the voltage gain. The converter has the advantages of high voltage gain, continuous input current, low voltage stress on the switch, and a common ground between the input power and the load. The theoretical analysis of the converter is carried out. Finally, the experimental prototypes of 300 W and 1000 W with the input voltage of 25V and output voltage of 400V are built. The experimental results verify the characteristics of the proposed converter as the ultra-high gain, continuous input current, and low voltage stress.
Medium-voltage (MV) silicon carbide (SiC) power devices are critical enablers for next-generation power grids and transportation systems. This article presents a 10-kV double-sided cooling (DSC) SiC MOSFET power module featuring embedded decoupling capacitors, co-packaged gate drivers, and direct water cooling. The proposed package employs a double-sided magnetic-field self-cancellation mechanism to minimize the power-loop parasitic inductance and integrates a common-mode (CM) screen to suppress CM electromagnetic interference (EMI). As a result, a low power-loop parasitic inductance of 5.1 nH is achieved. In addition, high-thermal-conductivity Cu-diamond interposers combined with integrated Pin-Fin heat sinks significantly reduce the thermal resistance and enhance the thermal performance. Double-pulse tests at a DC-link voltage of 5 kV show negligible voltage overshoot and ringing. At a dv/dt of 80 V/ns, the CM current is limited to 0.84 A. Thermal characterization indicates that the single-chip junction-to-fluid thermal resistance (Rth,j-f) is 0.295 K/W at a flow rate of 5 L/min. Finally, partial discharge (PD) tests confirm the robust insulation integrity of the module, which withstands an overstress voltage of 11.7 kVrms while maintaining a discharge magnitude of only 7.5 pC.
The low-frequency zero sequence circulating current (LF-ZSCC) in paralleled system is primarily induced by the common-mode voltage (CMV) differences between inverters. Conventional methods suppress LF-ZSCC by either calculating a desired reference CMV through communication or synthesizing virtual voltage vectors (VVs). However, the former suffers from poor reliability, while the latter is communication-independent but fails to achieve effective LF-ZSCC suppression due to dead-time effects and limitations in VV synthesis at high modulation index (MI). To address these issues, a low-frequency circulating current predictive control (LF-C2PC) is proposed in this article, where the dynamic model of ZSCC is employed in a communication-free manner to calculate the optimal reference CMV (OR-CMV). Based on the OR-CMV and reference current, two active vectors and two zero vectors are allocated hierarchically, which not only suppresses ZSCC, but also ensures precise current tracking. Furthermore, when the OR-CMV cannot be directly synthesized at high MI, a dynamic VVs allocation strategy is proposed to extend the effective synthesis range (ESR) of CMV, achieving superior ZSCC suppression. Finally, the effectiveness of the proposed LF-C2PC is verified through simulation and experimental results.
For grid-forming (GFM) converters with circular current saturation limiters, existing anti-windup methods lack wide-range tunability of the equivalent impedance in current-limiting mode (CLM), restricting the enhancement of transient stability. This letter proposes a cross-coupling back-calculation anti-windup (CC-BCAW) method for CLM impedance reshaping. By introducing a complex back-calculation gain, this method provides two degrees of freedom to flexibly adjust CLM equivalent impedance angle while ensuring a satisfactory anti-windup performance. Consequently, it achieves a larger transient stability margin than existing anti-windup methods with a simple control structure. Furthermore, the impacts of CC-BCAW parameters on small-signal stability, damping characteristics, and anti-windup dynamics are analyzed, and based on them the key parameter constraints are identified. Practical design guidelines are then provided by jointly considering transient-stability enhancement, GFM capability, small-signal performance, and anti-windup dynamics. Hardware-in-the-loop experiments validate the theoretical analysis, the effectiveness of the proposed method, and the rationality of the parameter design.
