In the field of aircraft assembly, the realization of automatic assembly inspection of aircraft parts is essential to improve aircraft assembly efficiency. However, how to identify each part accurately in a complex assembly scene is still a thorny issue. What's more, deep learning algorithms require large training datasets to converge. In this paper, the problems that are met in the recognition of aircraft cable brackets are analyzed in detail, and a region-based convolutional neural network is optimized by comparing different feature extractors and improving Feature Pyramid Network for small brackets. In addition, a simulation platform is developed based on the Unreal Engine to automatically generate synthetic realistic training datasets. Finally, take the task of inspecting cable brackets in the C919 aircraft as an example, experimental results show that the mAP@50 of the optimized model trained with the synthetic dataset is up to 96.3%.
Few-shot learning (FSL) has gradually become the most successful application of transfer learning. It focuses on classifying novel classes by only a few images, which do not appear in the training set. Among all kinds of few-shot learning methods, metric-based methods are the most widely used. It aims to learn representations of different categories and classify novel categories by measuring the distance between images and these representations. However, represented by prototypical networks, traditional metric-based methods usually calculate the category representation by overly simplistic approaches. To improve the accuracy of metric-based methods, we propose two models to learn a better representation for different categories: Normalized Prototypical Network (NPN) and Mixed Prototypical Classifier (MP). NPN is a complete network which performs better than many baselines of metric-based methods. MP is a classifier which can be combined with any metric-based model, it greatly improves the accuracy of the combined model on 1-shot FSL benchmarks. Experiments and ablation studies in MiniImageNet and CIFAR-FS prove the effectiveness of our methods.
Ship wake is an important military target, while the ocean background data in satellite images is huge, and ship wake targets are few. How to quickly and accurately find targets in large amounts of data is a valuable research topic. The ship wake target has a different detection method from the general target, as it has the characteristics of uniform background and prominent line characteristics. In this paper, we design a ship wake detection method which can quickly screen out easily detected samples by using traditional algorithms including Gaussian filtering, Canny edge detection and probabilistic Hough transform. We used typical representative YOLOv5 and Faster-R-CNN target detection frameworks to train single-stage and two-stage target detection models. In the process of integrating traditional algorithms into ship wake detection, we have built a ship wake target detection system that combines traditional algorithms with neural network methods. The experiment shows that the improved traditional wake detection algorithm can effectively improve the efficiency of ship wake detection system in target detection task.
Encryption has an important role in cloud computing, as it secures the data into a ciphertext which is then protected with public key. But, how to encrypt massive cloud data? Do we have an encryption scheme that allow computation on the ciphertext, thus make the ciphertext dynamically encrypted? A recent breakthrough Fully Homomorphic Encryption (FHE) by Gentry is so much fulfilled the requirement of cloud encryption. However, it requires a huge key size, thus encryption process takes long and impractical for real-time deployment. Hence, this work proposed FHE accelerator on hardware platform to speed up the encryption process so that practical encryption time could be achieved. We proposed an optimization on Digital Signal Processing (DSP) utilization on modern Field Programmable Gate Array (FPGA), Virtex7. Our proposed Karatsuba multiplier shows 15.94 times better Throughput vs Area than Comba Multiplier. With the significance performance, the proposed Karatsuba multiplier is then employed in the multiplication building block for FHE encryption process. A nearly practical encryption time is achieved between 0.005 s to 39.08 s for Toys to Large key size. In addition, our proposed multiplier has significantly small DSP usage, from 48 to 192 slices for Toys to Large key size.
The design architecture of backtracking calculation control processing for space large manipulator control is proposed. SRAM-type FPGA is used to build the hardware full three-mode computing core, and the processor architecture is designed based on FPGA. The register value and cache access value of the single instruction calculation process of the three computing processors are used to compare the three modes in the anti-fuse FPGA. At the same time, the results of three computing processors were compared by SPARC CPU. Fault backtracking calculation control, when a single computing module occurs an error, first detect the instruction execution position of the faulty module, and then carry out register-level data recovery for the faulty module, and restore to the instruction before the fault to accelerate the operation to complete the “backtracking” process, until the other two modules complete the calculation synchronization. According to the theoretical derivation and analysis, it is clear that under the linear increasing detection window, the maximum time of fault recovery is only related to the three-mode ratio transmission rate. According to this conclusion, the hardware digital logic design of the key modules of fault detection and recovery is carried out. The overall structure is simple and easy to implement, digital logic only occupies less than 100,000 logic gates. Compared with traditional methods, the fault recovery efficiency is improved by at least 90%.
