AI-enabled functions are increasingly considered for aerospace and other safety-critical systems, where predictable execution is as important as acceleration. Standard GPU programming models such as CUDA do not inherently provide the timing guarantees required for certification, since runtime jitter and limited worst-case predictability remain problematic. Vulkan SC has been proposed as a more deterministic alternative for safety-critical GPU execution. This work compares CUDA and Vulkan SC on the NVIDIA Jetson Orin Nano SoC platform with a focus on timing determinism. We apply fixed clocking, warm-up runs, and process-level optimizations. We then analyze timing contributions from memory management, data movement, and kernel execution. The evaluation covers neural-network-related synthetic primitives, composite SAXPY-ReLU chains, and a fused neural-network workload. To relate the synthetic primitives to the NN workload, we compare an operation-count-equivalent unfused primitive baseline with the measured fused implementation across input sizes. The results show that Vulkan SC provides more stable kernel execution and consistently low kernel-side jitter. The growth analysis shows that CUDA kernel time is nearly input-size independent for small and medium input sizes, while Vulkan SC shows less uniform growth. For both APIs, the unfused baseline remains above the fused NN kernel time, while the relative gap decreases with increasing input size. H2D/D2H transfer timing scales almost linearly with transferred data size for larger transfers, but remains a major source of end-to-end variability, especially for Vulkan SC. Overall, Vulkan SC improves kernel-level timing determinism, while system-level predictability remains constrained by transfer overhead and shared-memory effects.
Open-source operating systems, e.g., FreeRTOS and Zephyr, are developed by distributed communities that typically follow non-standardized, ad-hoc software development practices. This makes their adoption in safety-critical contexts particularly challenging, especially when targeting the highest safety assurance levels. This work presents a software architecture designed to remove the operating system from the safety rationale. This is accomplished by leveraging the stage-2 memory protection unit (MPU) available in the hypervisor mode of modern real-time processors. In contrast to existing (hypervisor-based) approaches, the proposed concept provides finer granularity by enabling the protection of individual applications rather than entire virtual machines. Our evaluation on the latest generation of NXP embedded SoCs (S32N family) shows that the combined overhead of control-flow interception and the reprogramming of the stage-2 MPU for each transition into and out of a safety-critical application is only about 0.5 s, which is comparable to typical interrupt path latencies. This indicates that the proposed scheme remains suitable even for low-latency, hard real-time applications.
Machine learning models for natural language processing have achieved remarkable performance across many domains, yet their adoption in safety engineering remains limited. A key barrier are hazardous failure conditions - such as hallucinations - which arise from an insufficient functionality of a foundation model system and must be controlled in safety-critical contexts. This article examines such behavior through a safety lens and traces root causes for obscure hazardous failure conditions in generic foundation model setups. From this analysis, we distill five broadly applicable concepts that provide a structured way to counter these challenges (narrow domain, setup diligence, uncertainty estimation and interpretability, iterative approaches, hybrid approaches). Together, they offer a principled starting point for deriving concrete design and assessment practices for safety engineers working with language-model-based systems. We illustrate our approach through three representative use cases that demonstrate how these five countermeasures can be applied in real-world safety engineering scenarios.
Integrating Machine Learning models within certified safety critical avionics systems faces several challenges among which we focus on the difficulty to demonstrate that a trained Machine Learning Model meets its requirements when deployed on the target system. Indeed, a semantic gap exists between training framework models and deployed inference models on target hardware. Certification standards require the rigorous implementation of ML model descriptions with design assurance, as well as a demonstration that properties verified during training (such as accuracy and robustness) are preserved on the target. To that end, we propose the Target Aware Training (TAT) approach, that ensures semantic preservation by construction. Practically, the training framework’s native inference engine is substituted with a compiled shared library derived from design-assured code for the target hardware. Doing so, we achieve bit-accurate replication and eliminate the need for error-prone transformations to and from intermediate representations like ONNX. The approach also allows the specification, control, and formal verification of activation and accumulator bounds. We validate our approach on the ResNet18 architectures, guaranteeing the absence of numerical overflows even for unseen data through a generative verification method. This dual contribution provides a robust path toward meeting DO-178C design assurance objectives for airborne ML applications.
Reliable Positioning, Navigation, and Timing (PNT) is a fundamental requirement for the safe operation of autonomous vehicles. While traditional GNSS-based PNT is typically very accurate in open sky conditions, its performance can degrade significantly in environments where satellite visibility is limited or signals are obstructed. To ensure continuity, it is beneficial to complement GNSS with other methods, such as AI-enhanced Visual SLAM, which remain robust under challenging environmental conditions. However, AI-based components can produce untrustworthy results and necessitate a safety cage to monitor and filter their output. This experience report presents the VAIPOSA architecture, which introduces a safety cage to perform runtime verification and fusion of hybrid GNSS and AI-based PNT sources. The safety cage monitors a variety of parameters, including GNSS signal characteristics, AI-based precision metrics, image quality, and vehicle state information, to determine the trustworthiness of each source. We describe the integration of these monitors within a supervisor that fuses data into a reliable pose estimate and discuss its validation in the CARLA simulator using automated test case generation and fault injection scenarios.
