The rapid proliferation of Internet of Things (IoT) devices has intensified the demand for ultra-low power and energy-efficient VLSI circuit designs. One of the major challenges in nanoscale CMOS technology is the significant increase in leakage power, which adversely affects battery life and system reliability in always-on IoT applications. This paper presents a low-leakage CMOS design using Dynamic Threshold Scaling (DTS) to effectively minimize static power dissipation while maintaining high performance. The proposed approach dynamically adjusts the threshold voltage (Vth_{th}th) of MOS transistors based on the operating conditions, enabling a trade-off between leakage reduction and switching speed. In the proposed architecture, adaptive body biasing and voltage control mechanisms are integrated to modulate the threshold voltage in real time. A 45 nm CMOS technology node is considered for implementation and simulation. Experimental results demonstrate that the proposed DTS-based CMOS design achieves a leakage power reduction of approximately 38.7%, along with a 22.5% improvement in energy efficiency compared to conventional fixed-threshold CMOS circuits. Additionally, the design maintains a delay variation within 8%, ensuring reliable performance for IoT workloads. The proposed method is particularly suitable for battery-operated and energy-constrained IoT devices such as wearable sensors, smart home systems, and remote monitoring units. Overall, this work provides a scalable and efficient solution for next-geerationn low-power CMOS circuit design in IoT ecosystems.
The rapid growth of energy-constrained applications such as Internet of Things (IoT), wearable electronics, and biomedical implants has intensified the need for ultra-low power circuit design methodologies. Subthreshold computing has emerged as a promising solution by operating transistors below the threshold voltage, significantly reducing dynamic power consumption. However, leakage currents become dominant in this regime, leading to degraded performance and reliability challenges. This paper presents a leakage-aware FinFET-based CMOS design framework optimized for sub-threshold computing applications. The proposed approach leverages the superior electrostatic control and reduced short-channel effects of FinFET technology to mitigate leakage currents while maintaining acceptable performance levels. A combination of adaptive threshold control, multi-fin optimization, and leakage reduction techniques such as gate work-function engineering and power gating is incorporated into the design. The proposed architecture is evaluated using standard benchmark circuits, demonstrating a significant reduction in leakage power by up to 35-45% compared to conventional planar CMOS designs, while maintaining competitive delay characteristics. Furthermore, the design shows improved energy efficiency and robustness against process variations, making it suitable for next-generation low-power embedded systems. The results highlight that FinFET-based CMOS circuits provide a viable pathway for achieving energy-efficient and reliable sub-threshold operation in modern nano-scale technologies.
This paper designs a W-band compressive imaging system using a flat metamaterial aperture to perform high-resolution imaging without mechanical scanning or costly phased arrays. The proposed system employs a 2D metamaterial-based parallel plate waveguide integrated with cELC elements, excited by frequency-diverse radiation patterns. By leveraging compressive sensing principles, the system reconstructs sparse scenes through a measurement model, which is considered as a linear inverse problem and regularized using prior sparsity constraints. Key metrics, including SVD spectra, MSE, and effective sparsity, are analyzed to optimize crucial parameters such as aperture density, bandwidth, element quality factor, and spatial distribution. Trade-off studies demonstrate quasi-linear performance dependence on frequency points and bandwidth, along with minimal sensitivity to element density. An experimental validation is conducted using a synthesized aperture with 43 receiver positions and a single transceiver. The obtained results demonstrates high consistency between the simulations and measured results, though target specularity limits the full resolution. Furthermore, effective sparsity is considered as a unified metric for system evaluation, demonstrating the feasibility of W-band metamaterial-based compressive imaging. This approach provides a cost-effective solution for millimeter-scale resolution in security, aerospace, ad industrial applications, allowing to balance nthe performance and practical implementation constraints.
Heat generated during charging and discharging cycles can degrade lithium-ion battery performance and lead to thermal runaway. This study presents an immersion liquid cooling system for prismatic lithium-ion energy storage battery modules, and evaluates its thermal performance through experiments and simulations. Experimental results indicated that natural air cooling allowed both the average module temperature and maximum temperature difference to exceed safe limits. Immersion cooling reduced the maximum temperature difference by 33.1% and the average temperature by 17.3% compared to natural cooling. Optimal thermal performance occurred at a coolant temperature of 25 degrees C and a flow rate of 1.75 L/min; further increases in flow rate or temperature reduced efficiency. To explore the influence of system design, numerical simulations using ANSYS Fluent integrated fluid-thermal coupling model and Battery heat generation model. This study investigated the effects of inter-battery spacing, tank dimensions, and novel structural designs. An 8 mm spacing provided the best compromise between flow behavior and heat transfer characteristics. Structural optimization of the immersion tank was found to reduce the maximum temperature difference across the module by up to 14.36%. An ejector-style inlet-outlet configuration combined with a layered design reduced the average temperature by 2.17 degrees C and decreased the maximum temperature difference by 36.34% compared with the initial case. These findings demonstrate that the optimized structural design can remarkably improve cooling performance, thereby offering a practical and viable solution for the immersion liquid cooling system of lithium-ion batteries.
Ruthenium (Ru) has emerged as a critical material for nanoscale interconnects in advanced integrated circuits due to its short electron mean free path (6.59 nm), high melting point (similar to 2334 degrees C), and superior electromigration resistance. As technology nodes scale toward 2 nm and below, conventional copper interconnects suffer from severe resistivity increases caused by size-dependent electron scattering. This review systematically examines the application progress of Ru in nanoscale interconnect technologies, including buried power rails, backside power distribution networks, and high-aspect-ratio via structures. Unlike copper, Ru eliminates the need for thick diffusion barrier layers such as Ta/TaN, reducing overall resistance and enabling direct integration with low-k dielectrics. Recent breakthroughs in grain boundary engineering, including atomic layer deposition combined with high-temperature annealing, have achieved Ru grain sizes exceeding 100 nm, reducing resistivity to near its theoretical limit (7.6 & micro;.s2 & centerdot; cm). Furthermore, Ru-based diffusion barriers (e.g., RuTiN, Ru-Mo-C, Ru-Mn) and seed layers have demonstrated exceptional performance in suppressing Cu diffusion and enhancing interfacial adhesion. Emerging applications in direct metal etching, airgap integration, self-aligned vias, and two-dimensional material heterojunctions (graphene, MoS2) are also discussed. Finally, this review summarizes current challenges in high-purity Ru preparation, compares chemical and physical synthesis routes, and outlines future directions for metastable phase engineering and low-dimensional Ru structures. The findings position Ru as a transformative material for sustaining nanoelectronic device scaling beyond the 5 nm node.
