As semiconductor technology scales, local layoutdependent effects (LLDEs) have become a significant factor in determining device performance, particularly in high-frequency RF applications. These effects often lead to significant discrepancies between schematic-level simulations and post-layout, leading to multiple design iterations. Additionally, the highdimensional nature of LLDE variables makes exhaustive design space exploration via traditional SPICE simulations computationally burdensome. This paper introduces Metrics-Net, a multimodal surrogate model that uses deep learning to predict transistor performance from layouts. By processing image and numerical inputs together-combining LLDEs reflected layout images with numerical design parameters- Metrics-Net provides rapid and accurate predictions of critical transistor metrics $f_{T}$, $f_{\text {max }}$, from S-parameters and $F_{\text {min }}$ from noise. Experimental results demonstrate that the proposed model achieves a 1,000fold speed increase over conventional SPICE-based extraction and simulation with high accuracy. This acceleration enables an efficient search of the vast design space, allowing layout-aware transistor optimization in the early stages of the design.
This paper presents a sub-THz communication link using a $\mathbf{1 6}-\mathbf{n m}$ FinFET direct-digital modulation transmitter and a 0.6 m circular hollow plastic (PTFE) waveguide. The transmitter performs high-order modulation directly at carrier frequencies and implements on-chip amplitude and phase calibration to mitigate I/Q mismatch. The transmitted signal is coupled from a rectangular metal waveguide into a circular hollow plastic waveguide through a probe antenna and a 3D stereolithography (SLA) printed resin coupler, enabling efficient mode conversion and low-loss propagation. The 0.6m prototype data link operates at D-band (140 GHz) and achieves 32 Gb/s 16-QAM data transmission with a measured EVM of -21.1 dB without extensive offline equalization. The transmitter has 235 mW DC power. The proposed system demonstrates the feasibility of using hollow plastic dielectric waveguides as a low-cost, high spectral efficiency, and energy-efficient interconnect solution for short-range sub-THz communication links.
This paper investigates a stealthy Trojan attack targeting the timer-based distributed retransmission mechanism of C-ARQ in energy-harvesting wireless networks. The attack subtly alters the timer of a compromised node, biasing retransmission selection and reducing its participation, which leads to energy imbalance, wasted energy, and degraded network performance. Experimental results show that at low energy harvesting rates, the attack can reduce the packet delivery ratio by up to 20%, demonstrating that even minor timer manipulations can significantly disrupt node selection. At higher energy harvesting rates, nodes maintain sufficient energy for retransmissions, reducing reliance on other nodes, including the compromised node, and thereby mitigating the attack’s effect and restoring network performance. These findings reveal a previously unexplored vulnerability in C-ARQ-based EH networks and underscore the need for robust, energy-aware mechanisms to ensure network reliability and resilience.
Real-time speaker verification (SV) on resource-constrained edge devices (smartwatches, hearables, and standalone meeting assistants) is attractive for privacy and responsiveness, yet the field’s shift toward large deep-learning (DL) speaker embeddings such as x-vectors and ECAPA-TDNN imposes memory and latency costs that are prohibitive for ultra-low-power microcontroller units (MCUs). Rather than contesting cloud-scale accuracy, the question addressed here is what verification quality is reachable under strict MCU limits. This work presents a profiling and analysis framework that evaluates 240 feature–classifier pipelines, comparing classical digital signal processing (DSP) features paired with lightweight classifiers and modern DL embeddings under a single-core, memory-bounded edge simulation. Each pipeline is scored for accuracy by its equal error rate (EER), latency by its real-time factor (RTF), and peak memory. Selection is posed first as a hard constraint-satisfaction problem (CSP) and then as a tunable multi-objective figure of merit (FOM) optimization problem. Although DL embeddings dominate raw accuracy, every embedding pipeline overruns the 256 KB budget, leaving 112 feasible DSP pipelines. Among these, a logistic-regression classifier on pooled mel-frequency cepstral coefficients (MFCCs) is the most preference-robust choice for 256 KB-class devices, at $\mathbf{1 6 . 6 \%}$ EER, 44 KB, and an estimated on-device RTF of 0.28. Personalizing per speaker further reduces mean EER to 5.95%.
Artificial intelligence (AI) based applications are becoming increasingly integrated into everyday life; however, the computational cost of executing AI training is becoming a challenge, mostly due to the delay and power consumption from large data movement from memory devices. Resistive Random Access Memory (RRAM) has shown promising results by enabling in-memory computing, hence alleviating the data-movement bottleneck. This paper presents a detailed design for the RRAM unit cell as well as RRAM array peripheral circuit architecture for memory computation using a silicon-proven 4Kb (64 × 64) 1T1R RRAM array in a 65 nm CMOS technology node. This work paves the path for design and hardware implementation of custom RRAM-based AI accelerators.
