This work presents new hardware architectures for AES-128 encryption tailored to resource-constrained IoT devices. We propose 32-bit and 64-bit round-based designs that significantly increase throughput while maintaining an efficient area–performance balance. Each datapath includes an independent key schedule module capable of generating multiple round key bytes per cycle in parallel with encryption, eliminating key-setup latency. Both architectures use the lightweight S-box [11] and are synthesized in STM 65 nm CMOS technology for fair comparison with the 16-bit baseline in [2]. The proposed 32-bit and 64-bit designs reduce encryption latency to 44 and 22 cycles per 128-bit block and increase throughput from 734 Mbps to 1.512 Gbps and 2.950 Gbps, corresponding to improvements of 106 × and 2.18 × higher efficiency than the baseline. Compared to designs in [13], they achieve lower latency with fewer S-boxes, resulting in smaller area and higher throughput. These features make the architectures well suited for low-latency, energy-efficient AES implementations in IoT hardware.
Let q be an odd prime power and let 𝔽_q denote the finite field with q elements. We study the functional graph structure of the polynomial map F(X) = (aX^q + bX)(X^q - X)^n-1 over the quadratic extension 𝔽_q^2 , building on the dynamical analysis of Brochero and Teixeira. By representing 𝔽_q^2 as a two-dimensional vector space over 𝔽_q , we obtain an explicit coordinate form for F that reveals how the parameters a, b, and n control the preimage structure. We introduce three parameterized families of functions derived from F with controlled preimage properties: the first achieves constant preimage size (n,q-1) for non-zero elements when a^2 b^2 ; the second incorporates affine shifts to avoid degenerate orbits; and the third projects to a one-dimensional setting. We analyze the cycle structure, connected components, and trees attached to cycles in each case. As an application, we observe that these families satisfy the conditions for ϵ -strongly universal hash functions, suggesting potential use in randomized algorithms and data structures. We aim to connect the rich theory of functional graphs over finite fields with parameterized function families having predictable combinatorial behavior.
The security of multivariate public-key cryptography, a major approach to post-quantum cryptography, is based on the computational hardness of solving systems of multivariate quadratic equations over finite fields (the MQ problem). The MQ problem consists of solving a system of quadratic equations over a finite field of size q, with n variables and m polynomials. The existence probability of solutions to the MQ problem plays a central role in analyzing the security of multivariate cryptography. However, explicit bounds for fixed parameters (q, n, m) have not been sufficiently studied. In this work, we evaluate the existence probability for randomly generated MQ systems with fixed parameters by analyzing the coefficient space arising from the MQ system. Using the inclusion–exclusion principle, we obtain a lower bound (approximately 0.625) and an upper bound (approximately 0.667) on the existence probability, focusing on the case m=n . We also derive upper and lower bounds on the probability that the number of solutions is exactly one in the case m=n . Finally, we analyze the existence probability of solutions to the MQ problem in the case m n .
This paper investigates the design of a Polynomial Modular Number System (PMNS) for 256-bit prime field arithmetic on 8-bit architectures. To fit coefficients into 8-bit words, we target a basis matrix B with B _1<2^8 and dimension n>31 . We first demonstrate that standard LLL reduction is effective, achieving this 8-bit target for a wide range of parameters and approaching the heuristic theoretical limits for small γ . However, for large γ or as the dimension grows, a gap emerges between LLL’s output and the theoretical minimum. We prove the existence of a global minimum and propose a local-improvement framework using Integer Linear Programming (ILP). This work establishes LLL as a powerful initializer and provides a principled algorithmic foundation for purpose-specific PMNS optimization.
Many True Random Number Generators (TRNGs) extract randomness from a jittered clock generated by an oscillator either by directly sampling this clock (in sampling mode) or by counting the number of samples equal to one during a reference interval (in counting mode). This architectural choice has a decisive impact on the statistical quality of the output bit stream. Previous works suggest that counting provides an advantage over sampling mode, arguing that jitter accumulation over many oscillator periods yields higher entropy per output bit. The aim of this work is to study both methods more closely using a unified framework of standard random tests. We analyze experimental data acquired from the two TRNG configurations implemented in a Field Programmable Gate Array (FPGA) in self-timed rings (STR). The results show that the sampling method produces higher correlation values that are consistent with other tests: Markov chains, run length, balance, etc. Additionally, we provide results over free running oscillator-based TRNG architectures and we derive experimental limits of the parameters of the two TRNG configurations.
