Efficient Logic Evaluation Using RRAM-Based In-Memory Computing

In recent years, in-memory computing has been extensively utilized for data-intensive applications due to its high speed and energy efficiency. Various memory technologies have been explored for this purpose, with Resistive Memory (RRAM) standing out due to its ability to naturally implement MultiplyAccumulate (MAC) operations, making it a promising solution for neural network acceleration. Additionally, RRAM is also applied in general logic computing applications. However, RRAM-based logic in-memory computing faces notable challenges, such as the need for repeated write operations, which leads to high latency and energy inefficiency. Furthermore, synthesized circuits often require mapping into large crossbars, reducing area efficiency. In this work, we introduce a novel logic in-memory computing framework designed to address these issues. Our proposed framework transforms the logic evaluation of AndInverter Graphs (AIGs) into MAC operations and binary step functions. This method eliminates the necessity for frequent write operations during the computing phase, thereby enhancing operational efficiency. Additionally, we propose two optimization techniques to achieve better area efficiency. Simulation results demonstrate that our proposed computing framework can perform logic evaluation without the need for writing during the computing phase. Furthermore, it achieves an average reduction of 86.13% in the Area-Latency-Product (ALP), a key metric for logic evaluation, compared to traditional designs.