Techniques for Debug of Low Power SoCs

With the ever-increasing demand for portable electronic devices to provide longer battery life, extremely low power consumption becomes an SoC design imperative. Aggressive SoC and system-level power management methods (PMM) are key to this drive towards low power consumption and extended battery life. These methods pose many challenges to the validation of the low-power states, SoC and system-level debug, and overall product time to market (TTM). This paper discusses techniques developed to address these SoC validation and debug challenges efficiently.