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    专

    Detection of immunoglobulin free light chain (FLC) dimers in sample comprises e.g. subjecting sample to proteolytic digestion under non-reducing conditions, thus obtaining digested sample.

    6908002681A1
    发明人
    LIYASOVA M, MA B
    受让人
    RAPID NOVOR INC (RAPI-Non-standard)
    申请人
    Jean-Young Jang, Jong-In Choi, Hae-Souk Cho, Sung-Kyun Yoon, Jae-Yoon Shim, Heon-Su Kim, Toniolo Luigi, Vavasori Andrea
    申请号
    004080
    申请日
    1977-11-29
    公开(公告)号
    6908002681A1
    公开(公告)日
    2008-06-24
    IPC分类号
    A01K001/00A01K029/00
    CPC分类号
    -
    优先权号
    164276P
    618443
    730818
    优先权日
    2009-03-26
    2009-11-12
    2010-03-23
    摘要

    NOVELTY - Preparation of a deodorized and stabilized food-grade marine oil involves submitting a marine oil to a counter-current steam distillation (CCSD) in a thin film column containing a structured packing and optionally adding antioxidant(s).

    USE - In the manufacture of dietary or health supplements, fortified food and feed (functional food/feed) as well as cosmetic product or pharmaceutical preparations (claimed).

    ADVANTAGE - The method provides removal of 2,6-nonadienal, 3,6-nonadienal and 4-heptenal which are essential molecules that contribute to the unwanted smell and/or reduced stability in marine oils. The deodorized and stabilized food-grade marine oil are measured in fatty acid smell and test (FAST) index of below 1.5 (preferably 1.3-1, especially 1.1-1, particularly 1). The rancimat induction time value of more than 6.2 (preferably 10.5-20) hours.

    DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for production of a dietary, health or nutritional supplement or fortified/functional food rich in n-3 polyunsaturated fatty acids, from an intermediate food or its components involving adding to it/them an amount of the marine oil in liquid form or in form of an emulsion or gel or in dry form containing the desired amount of n-3 fatty acid(s), dispersing it by intensive mixing and optionally, further processing and post-processing the blend.

    权利要求
    45. A circuit comprising: +P1 A. a data input lead; +P1 B. a test data input lead; +P1 C. a data output lead; +P1 D. a test data output lead; +P1 E. a first multiplexer having an input connected to the data input lead, an input connected to the test data input lead and an additional input and having one output; +P1 F. a first memory having an input connected to the output of the first multiplexer and having an output connected to the additional input of the first multiplexer and to the test data output lead; +P1 G. a second memory having an input connected to the output of the first memory and having an output; and +P1 H. a second multiplexer having an input connected to the data input lead and an input connected to the output of the second memory, and having an output connected to the data output lead:
    46. The circuit of claim 45 in which the circuit is a test cell.
    47. The circuit of claim 45 in which the circuit is a boundary scan test cell.
    48. The circuit of claim 45 in which an output of the second memory is connected to the input of a multiplexer.
    49. The circuit of claim 48 in which the output of the second memory connected to the input of a multiplexer is a second output of the second memory and the multiplexer is the first multiplexer.
    50. The circuit of claim 48 in which the output of the second memory connected to the input of a multiplexer is connected to the input of the first multiplexer.
    51. The circuit of claim 45 in which the test data input lead is a serial test data input lead and the test data output lead is a serial test data output lead.
    52. The circuit of claim 45 in which the first multiplexer has two control inputs.
    53. The circuit of claim 45 in which the second multiplexer has one control input.
    54. The circuit of claim 45 including an input buffer coupled to the data input lead and application logic coupled to the data output lead.
    55. The circuit of claim 45 including application logic coupled to the data input lead and an output buffer coupled to the data output lead.
    56. The circuit of claim 45 in which the first multiplexer has two stages, the first stage has a data input connected to the data input lead, a test data input connected to the test data input lead, a control input and an output, the first stage has transistors connected to the control input and selectively connecting only one of the data input and the test data input to the output of the first stage.
    57. The circuit of claim 45 in which the first multiplexer has two stages, the second stage has two sets of transistors, a control input is connected to the two sets of transistors and the output of the second stage is coupled to the output of the first multiplexer, one set of transistors selectively connects one of the data input lead and the test data lead to the output of the multiplexer and the other set of transistors selectively connects the output of the first memory to the output of the first multiplexer.
    58. The circuit of claim 56 in which each set of transistors forms a transmission gate.
    59. The circuit of claim 45 in which the first memory is a D-type flip flop.
    60. The circuit of claim 45 in which the first memory includes two sets of inverters, each set includes two inverters having an output of one inverter connected to the input of the other inverter, and includes at least one transistor between the input of the first memory and a first set of inverters and at least one transistor between the sets of inverters.
    61. The circuit of claim 45 in which the second memory includes at least one set of inverters, each set includes two inverters having an output of one inverter connected to the input of the other inverter, and includes at least one transistor between the input of the second memory and a first set of inverters.
    62. A boundary scan test cell circuit comprising: A. a data input lead; B. a test data input lead; C. a data output lead coupled to the test data input lead; D. a test data output lead; E. a first multiplexer having an input connected to the data input lead, an input connected to the test data input lead, and an additional input and having one output; F. a first memory having an input connected to the output of the first multiplexer and having an output connected to the additional input of the first multiplexer and to the test data output lead.
    63. The circuit of claim 62 in which the test data input lead is a serial test data input lead and the test data output lead is a serial test data output lead.
    64. The circuit of claim 62 in which the first multiplexer has two control inputs.
    65. The circuit of claim 62 including an input buffer coupled to the data input lead and application logic coupled to the data output lead.
    66. The circuit of claim 62 including application logic coupled to the data input lead and an output buffer coupled to the data output lead.
    67. The circuit of claim 62 in which the first multiplexer has two stages, the first stage has a data input connected to the data input lead, a test data input connected to the test data input lead, a control input and an output, the first stage has transistors connected to the control input and selectively connecting only one of the data input and the test data input to the output of the first stage.
    68. The circuit of claim 62 in which the first multiplexer has two stages, the second stage has two sets of transistors, a control input is connected to the two sets of transistors and the output of the second stage is coupled to the output of the first multiplexer, one set of transistors selectively connects one of the data input lead and the test data lead to the output of the multiplexer and the other set of transistors selectively connects the output of the first memory to the output of the first multiplexer.
    69. The circuit of claim 68 in which each set of transistors forms a transmission gate.
    70. The circuit of claim 62 in which the first memory is a D-type flip flop.
    71. The circuit of claim 62 in which the first memory includes two sets of inverters, each set includes two inverters having an output of one inverter connected to the input of the other inverter, and includes at least one transistor between the input of the first memory and a first set of inverters and at least one transistor between the sets of inverters.
    说明书
    [0001]REFERENCE TO RELATED APPLICATIONS
    [0002]This application claims the benefit of the earlier filing date of U.S. Provisional Application Ser. No. 61/962,623 filed on Nov. 12, 2013.
    [0003]STATEMENT CONCERNING GOVERNMENT INTEREST
    [0004]None.
    [0005]BACKGROUND OF THE INVENTION
    [0006]1. Field of the Invention
    [0007]The present invention relates to a clamping support structure useful in simulating a necktie, and more particularly to a nested set of conical segments which capture the edges of variously colored fabric to simulate the appearance of a necktie knot of one selected texture and color that is then combined to appear as a knot forming part of a necktie comprising distinctly different textures and/or colors.
    [0008]2. Description of the Prior Art
    [0009]A common appearance of one's attire, personal ornamentation, or most frequently a necktie, are often adopted as identifying symbols, or distinctive markings, by various groups like fraternal organizations, sororities, youth organizations, student groups attending a particular school, and the like, in order to quickly distinguish their members by a unique and highly visible symbol. While sometimes used as uniforms, distinctly marked, articles of clothing are prone to progress towards our functional needs, leaving this distinguishing task to the last non-functional item, a necktie, which few have learned to properly tie, and even when its knotting is learned, leave limited options for combining visible texture and color combinations that are contrasted right at the edges of the knot.
    [0010]In the past various mechanisms have been proposed which in one way or another seek to assist those unfamiliar with in the forming of a proper necktie knot exemplified by the teachings of U.S. Pat. No. 5,416,926 to Koy, U.S. Pat. No. 5,953,755 to Barylski, U.S. Pat. No. 6,094,746 to Miller, and others; illustrate structures that simply simulate a knot, as in U.S. Pat. No. 6,691,319 to Simon, U.S. Pat. No. 6,920,642 to Dickens, and others; or reform the necktie knot in a manner where it remains permanently tied while still allowing the necktie to be put on and removed, as in U.S. Pat. No. 3,737,917 to Orr. Each of the foregoing, while suitable for the purposes intended, provide little or no convenient facility to combine various colors and textures in a single necktie with the contrasting combination edges aligned right at the edges of the knot, to form a crisp delineation between the several colors and textures forming a symbolically distinctive article of clothing that emphasize the familiar shape of a necktie by its contrasting alignments.
    [0011]A necktie knot shaped nested assembly that conveniently captures the edges of a cloth covering segment to create the appearance of a knot together with other fabric pieces shaped as the descending portion of the tie along with a neck strap is therefore extensively desired and it is one such assembly that is disclosed herein.
    [0012]SUMMARY OF THE INVENTION
    [0013]Accordingly, it is the general purpose and object of the present invention to provide a structure facilitating the assembly of various fabric pieces into a necktie by capturing the separate tie ends and the edges of a fabric piece forming the knot appearance between conformingly nested pieces to simulate a knotted necktie.
    [0014]Other and further objects of the invention shall become apparent upon the examination of the description that follows in conjunction with the illustrations appended.
    [0015]Briefly, these and other objects are accomplished within the present invention by providing a nested set of generally C-sectioned, longitudinally tapered interlocking conical segments or pieces between which both the end panels or straps of a necktie are captured together with the edges of a separate fabric panel covering the exterior piece to simulate the decorative aspects of a distinctly colored and textured necktie knot. The internally captured strap end portions of the tie may be joined together at a stiffened segment of a conforming planform that is receivable between the nested segments with the narrower strap then looped back to extend as an adjustable neck strap that is frictionally retained by the nested compression but nonetheless left sufficiently free to allow for a fitted adjustment around the wearer's neck.
    [0016]Preferably each of the tapered and nested pieces is formed of a bendable sheet metal structure like sheet aluminum which once assembled in their nested form are then each pierced by a common drilling through which a fastening pin of a broche or medal is then passed once the necktie is assembled. It will be appreciated that the nesting offset of this common opening that results from the thickness increase attributable to the captured tie and knot fabrics will also provide a clamping effect, thus insuring a secure component engagement while still allowing strap adjusting movement for a good fit.
    [0017]In this manner various color and texture combinations can be repeated to achieve a uniformly distinct necktie that can be conveniently assembled by those joining a group by way of an assembly facilitated by a minimal nested structure that is then fixed together by a pin that may also serve as an attachment for additional decorative items or insignia indicating tenure or rank.
    [0018]BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective illustration, separated by parts, of the inventive necktie simulating assembly; FIG. 2 is a further perspective illustration of the inventive necktie simulating assembly shown in FIG. 1 depicting the receiving side of the exterior piece of a nested support structure; FIG. 3 is yet another perspective illustration of the inventive necktie simulating assembly in its completed form; and FIG. 4 is a sectional view taken along line 4 - 4 of FIG. 3 , illustrating the engaged components of the inventive necktie simulating assembly.
    [0019]DESCRIPTION OF THE PREFERRED EMBODIMENT
    [0020]As shown in FIGS. 1 through 4 , the inventive necktie simulating assembly generally designated by the numeral 10 comprises an outer and inner, generally tapered frustoconical panel segment or piece 11 - o and 11 - i each provided with rolled-over lateral edges LE-o and LE-i dimensioned to define a space or gap between them that is conformed for a substantially matching nested receipt of the inner piece 11 - i within the outer piece 11 - o . Preferably, each of the nested pieces 11 - o and 11 - i are formed by rolled bending of corresponding generally trapezoidal exterior and interior metal panels, or sheets, to define a hollow interior space of a generally tapered conical frustum with the edges LE-o and LE-i of each panel, when nested in their frustoconical shape, overlying each other to define an access gap into the enclosed space which, on its panel exterior, approximates the general shape of a well-formed necktie knot.
    [0021]In this form the nested combination of the inner and outer pieces is useful to grasp the peripheral edges 12 E of a generally trapezoidal fabric piece 12 of planform dimensions greater than the panel planform of the outer piece 11 - o where it remains captured between the outer piece and the inner piece 11 - i to cover the outer piece with a separate fabric covering that is distinct from the remaining parts of the tie to present the appearance of a distinctly appearing tie knot that is crisply distinguished from the rest of the tie. To achieve the full benefit of this visual appearance a differently colored and textured tie end TE and strap ST are then each stitched at their hidden portions to one side of a common trapezoidal fabric piece 14 with the strap ST then looped back onto the other side of piece 14 to form a loop when the piece captured by the inner piece 11 - i.
    [0022]It will be appreciated that the tapering nested fit of the inner piece 11 - i within the outer piece 11 - o will produce an increasing capturing force between them as the inner piece is advanced further into the outer piece. Thus a predictably secure capturing engagement retaining the covering cloth 12 edges 12 E, the fabric piece 12 and the tie end TE can be achieved by way the positioning of alignment drillings 15 - o and 15 - i respectively in the outer piece 11 - o and the inner piece 11 - i through which a common fastening pin 16 P of a broche or insignia 16 is inserted to be then secured by a securement clip 17 , thus aligning the desired depth of nested receipt and therefore the lavel of capturing retention. Of course, the off-center alignment of the strap ST assures that its adjustable function remains in tact, allowing for the adjustment convenience assuring a comfortable fit around the user's neck.
    [0023]In this manner a well defined color and texture combination of a necktie is assured which, in view of the generally fixed structure of the knot defining portion repeatably assures a well-formed knot of one selected texture and color that is then combined with a tie end of the desired distinct texture and color to properly distinguish a fraternal organization, a business enterprise and so on. Significantly, this same distinct appearance is always associated with a well-formed and neatly defined knot.
    [0024]Obviously many modifications and variations of the instant invention can be effected without departing from the spirit of the teachings herein. It is therefore intended that the scope of the invention be determined solely by the claims appended hereto.
    同族专利
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