• 学术搜索
  • 科研智能体
    • Research Labs
    • AI 阅读
    • AI 文库
    • 深度研究
    • 学者亮点
  • 学术资源
    • AI2000
    • 期刊/会议
    • 学者库
    • 学术API
    • 溯源树
    • 数据集
  • 知识沉淀
    • 学术空间
订阅小程序
旧版功能
aminer vip
开通会员低至0.73元/天
一次搞定AI科研
立即登录
  • English
    • 联系方式
    专

    一种面向天地一体化场景的智能时隙分配方法及系统

    1261020200064482B
    发明人
    李晓倩, 徐孟颖, 秦爽, 冯钢
    受让人
    UESTC
    申请人
    KIM WU CHAN
    申请号
    3712589
    申请日
    1972-06-07
    公开(公告)号
    1261020200064482B
    公开(公告)日
    2024-10-09
    IPC分类号
    A01B063/114
    CPC分类号
    -
    优先权号
    324253
    优先权日
    1992-12-02
    摘要

    In a display assistant device, a speaker is mounted in a waveguide structure which is at least partially disposed beneath a display screen. The waveguide structure is mounted in an exterior housing which includes speaker grills distributed on a plurality of surfaces of the exterior housing, permitting sound waves from the speaker to be projected outside the exterior housing. A cover structure is disposed on top of the waveguide structure to conceal the waveguide structure and speaker within the exterior housing. The cover structure has a tilted bottom surface configured to be suspended above the waveguide structure and to be separated by a first space. Sound waves projected from an upper portion of the speaker are reflected by the tilted bottom surface and are guided through the first space to exit the device from a speaker grill portion located on a rear side of the exterior housing.

    权利要求
    1 . An apparatus for wireless power reception comprising: a rectifier configured to convert an alternating current voltage into a direct current voltage for a load coupled to the apparatus; a receiver coil and a resonant capacitor connected in series, a combination of the receiver coil and the resonant capacitor connected between two inputs of the rectifier; a first capacitor and a first switch connected in series, a combination of the first capacitor and the first switch connected in parallel with the resonant capacitor; and a second capacitor and a second switch connected in series, a combination of the second capacitor and the second switch connected in parallel with the resonant capacitor, the first switch and the second switch configured to adjust an impedance coupled to the receiver coil, the impedance associated with an Amplitude Shift Keying (ASK) modulation used by the apparatus.
    2 . The apparatus of claim 1 , wherein the first switch and the second switch are configured to provide a plurality of impedances coupled to the receiver coil using different ON and OFF combinations, and wherein the plurality of impedances includes at least a first impedance associated with a High state of the ASK modulation and a second impedance associated with a Low state of the ASK modulation.
    3 . The apparatus of claim 1 , wherein: the first switch is a first field-effect transistor (FET); the second switch is a second FET; the first FET and the second FET are configured to provide a plurality of impedances coupled to the receiver coil using different configurations; at least one of the first FET and the second FET is configured to operate in an ohmic mode; and the plurality of impedances includes at least a first impedance associated with a High state of the ASK modulation and a second impedance associated with a Low state of the ASK modulation.
    4 . The apparatus of claim 3 , wherein each of the first FET and the second FET is configured to switch configuration when a drain-source voltage of the each of the first FET and the second FET is close to 0.
    5 . The apparatus of claim 1 , further comprising a third capacitor and a third switch connected in series, a combination of the third capacitor and the third switch connected in parallel with the resonant capacitor.
    6 . The apparatus of claim 1 , wherein the first switch and the second switch are configured to adjust the impedance coupled to the receiver coil in accordance with measurements of an output voltage of the rectifier.
    7 . The apparatus of claim 1 , wherein the receiver coil is a variable inductor, and wherein the impedance associated with the ASK modulation is further adjusted by changing an inductance of the receiver coil.
    8 . The apparatus of claim 1 , wherein the apparatus is included in a wireless power transfer system, and wherein the wireless power transfer system further includes a transmitter, a transmitter coil of the transmitter magnetically coupled to the receiver coil.
    9 . A method comprising: connecting a receiver coil and a resonant capacitor in series; connecting a combination of the receiver coil and the resonant capacitor between two inputs of a rectifier, the rectifier configured to convert an alternating current voltage into a direct current voltage for a load of a wireless power transfer system; connecting a first capacitor and a first switch in series and connecting a combination of the first capacitor and the first switch in parallel with the resonant capacitor; connecting a second capacitor and a second switch in series and connecting a combination of the second capacitor and the second switch in parallel with the resonant capacitor; and configuring the first switch and the second switch to adjust an impedance coupled to the receiver coil, the impedance associated with an Amplitude Shift Keying (ASK) modulation used by the wireless power transfer system.
    10 . The method of claim 9 , wherein the first switch and the second switch are configured to provide a plurality of impedances coupled to the receiver coil using different ON and OFF combinations, and wherein the plurality of impedances includes at least a first impedance associated with a High state of the ASK modulation and a second impedance associated with a Low state of the ASK modulation.
    11 . The method of claim 9 , wherein: the first switch is a first field-effect transistor (FET); the second switch is a second FET; the first FET and the second FET are configured to provide a plurality of impedances coupled to the receiver coil using different configurations; at least one of the first FET and the second FET is configured to operate in an ohmic mode; and the plurality of impedances includes at least a first impedance associated with a High state of the ASK modulation and a second impedance associated with a Low state of the ASK modulation.
    12 . The method of claim 11 , wherein each of the first FET and the second FET is configured to switch configuration when a drain-source voltage of the each of the first FET and the second FET is close to 0.
    13 . The method of claim 9 , further comprising: connecting a third capacitor and a third switch in series; and connecting the third capacitor and the third switch in parallel with the resonant capacitor.
    14 . The method of claim 9 , wherein the first switch and the second switch are configured to adjust the impedance coupled to the receiver coil in accordance with measurements of an output voltage of the rectifier.
    15 . A controller circuit of a wireless power reception system comprising: a first switch and a second switch, the first switch connected in series with a first capacitor, the second switch connected in series with a second capacitor, wherein: a combination of the first switch and the first capacitor is connected in parallel with a resonant capacitor, a series combination of the resonant capacitor and a receiver coil of the wireless power reception system connected between two inputs of a rectifier of the wireless power reception system; a combination of the second switch and the second capacitor is connected in parallel with the resonant capacitor; and the first switch and the second switch are configured to adjust an impedance coupled to the receiver coil, the impedance associated with an Amplitude Shift Keying (ASK) modulation used by the wireless power reception system.
    16 . The controller circuit of claim 15 , wherein the rectifier is configured to convert an alternating current voltage into a direct current voltage for a load coupled to the wireless power reception system.
    17 . The controller circuit of claim 15 , wherein the first switch and the second switch are configured to provide a plurality of impedances coupled to the receiver coil using different ON and OFF combinations, and wherein the plurality of impedances includes at least a first impedance associated with a High state of the ASK modulation and a second impedance associated with a Low state of the ASK modulation.
    18 . The controller circuit of claim 17 , wherein: the first switch is a first field-effect transistor (FET); the second switch is a second FET; the first FET and the second FET are configured to provide a plurality of impedances coupled to the receiver coil using different configurations; at least one of the first FET and the second FET is configured to operate in an ohmic mode; and the plurality of impedances includes at least a first impedance associated with a High state of the ASK modulation and a second impedance associated with a Low state of the ASK modulation.
    19 . The controller circuit of claim 18 , wherein each of the first FET and the second FET is configured to switch configuration when a drain-source voltage of the each of the first FET and the second FET is close to 0.
    20 . The controller circuit of claim 15 , wherein the first switch and the second switch are configured to adjust the impedance coupled to the receiver coil in accordance with measurements of an output voltage of the rectifier.
    说明书
    [0001]CROSS REFERENCE TO RELATED APPLICATION This application is a divisional of application Ser. No. 10/485,139 filed Sep. 2, 2004 now U.S. Pat. No. 7,053,480 entitled “METHOD FOR TESTING A CHIP WITH A PACKAGE AND FOR MOUNTING THE PACKAGE ON A BOARD”.
    [0002]BACKGROUND OF THE INVENTION The invention relates to the field of semiconductor packaging and testing, and in particular to mounting an integrated circuit that has been tested on a board, wherein the adjacent connecting pins of the integrated circuit are in an inline arrangement. In order to keep the dimensions small for the package of a chip with multiple connecting pins (e.g., 88 pins), the connecting pins are arranged in line as close as possible. However, a minimum spacing must still be maintained since the space between associated holes on a board for insertion of the connecting pins may not be arbitrarily reduced. As the spacing of the holes and conducting lines on the board becomes closer, the process of fabricating a board becomes more complex and expensive. In addition, there is the risk that close spacing of the holes on the board will cause the connecting pins to short out during the soldering process. One technique for increasing hole spacing on the board is to configure the connecting pins of the package by bending some of the connecting pins or, for example, by inwardly offsetting every second connecting pin. However, the advantage of greater hole spacing on the board is counteracted by the disadvantages of requiring a special test socket to test the chips and requiring an expensive packaging mechanism. Specifically, the packaging mechanism must be designed such that the connecting pins are not bent out of their precise alignment. Therefore, there is a need for a method of testing and mounting the package on a board in such a way that simple and inexpensively produced test sockets are sufficient for testing, and similarly simple and inexpensively produced packaging mechanisms are sufficient for packaging, while at the same time achieving an offset arrangement for the connecting pins.
    [0003]SUMMARY OF THE INVENTION Briefly, according to an aspect of the invention, an integrated circuit that includes a die mounted within a package containing a plurality of input/output pins is tested by placing the integrated circuit into a test socket of automatic test equipment. Prior to the tested integrated circuit being mounted on a board, a portion of the plurality of input/output pins are bent from their inline position to an offset position. The integrated circuit with its inline connecting pins is inserted into a test socket for testing. At least one connecting pin is bent inward using a bending tool immediately before insertion of the connecting pins of the integrated circuit into the holes of the board, in order to achieve an offset arrangement of the connecting pins. The integrated circuit includes inline connecting pins (i.e., individuals skilled in the art frequently use the expression “dual inline”), and the integrated circuit is tested in this state. The integrated circuit to be tested is inserted into a test socket. A first advantage is that relatively inexpensive test sockets may be utilized to test the chips. A second advantage is that even inexpensive packaging mechanisms are sufficient for storing and transporting the chips. Additionally, at least one connecting pin, preferably every second connecting pin, is bent inward by the bending tool immediately before insertion of the connecting pins of the integrated circuit into the board in order to form an offset arrangement of the connecting pins. The invention thus combines the advantages of a package in which its connecting pins are in an inline arrangement with those of a package in which its connecting pins are in an offset arrangement. Electrical testing of the chip may thus be of a simple design since inexpensively produced test sockets are sufficient for the task. In addition, standard packaging mechanisms may be employed to package the package. Subsequent alignment of the connecting pins is simplified since the connecting pins are not bent into the offset arrangement until immediately before insertion into the board, rather than at the fabrication stage of the package. These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.
    [0004]BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a flowchart illustration of a method of testing an integrated circuit and bending selected external input/output pins of the integrated circuit and mounting the integrated circuit with selected external input/output pins bent an angle with respect to the inline position of the pins; FIGS. 1B-1F are simplified illustrations of the integrated circuit during the steps illustrated in FIG. 1A ; FIG. 2 is a top view illustration of an embodiment of a package with the bending tool attached; FIG. 3 is a front view illustration of the package of FIG. 2 with the bending tool attached; FIG. 4 is a front view illustration of an embodiment of a package; FIG. 5 is a section view of a board having holes for the connecting pins; and FIGS. 6A-6D illustrate another example of an integrated circuit.
    [0005]DETAILED DESCRIPTION OF THE INVENTION FIG. 1A is a flow chart illustration of a method 100 for testing an integrated circuit, bending the pins of the integrated circuit and mounting the integrated circuit. FIGS. 1B-1F are simplified sectional views of the integrated circuit during the steps illustrated in FIG. 1A . Referring to FIGS. 1A-1F , in step 102 inline connecting pins 1 of an integrated circuit that includes a die (not shown) and a package 2 containing the die, are input to a test socket 3 as shown in FIG. 1B . In step 104 , any rework that may be required on the package 2 or the chip is performed. The package 2 is then placed in a packaging mechanism such as a guide brace 4 and shipped in step 106 . Immediately before the package 2 is mounted on a board 5 , every second connecting pin 12 , for example, is bent inward by a bending tool 6 , while the remaining connecting pins 11 are left unmodified. The connecting pins 11 and 12 are inserted into associated holes 71 - 72 of the board 5 , preferably, by the bending tool 6 . FIG. 2 is a top view illustration of the package 2 , along with the connecting pins 11 and 12 , and with the bending tool 6 attached. FIG. 3 is a front view illustration of the package 2 with the connecting pins 11 and 12 , and with the bending tool 6 attached. Every second connecting pin 12 is bent inward, while the remaining connecting pins 11 remain bent outward or are oriented vertically, as is the case during fabrication of the package 2 . FIG. 4 is a front view of the package 2 , with the first connecting pins 11 bent outward and the second connecting pins 12 bent inward, including dimensional details. The spacing between the vertical pins on the package is 19.05 mm. The second connecting pins 12 are bent 0.4 mm inward from the vertical, while the first or remaining connecting pins 11 are bent 0.87 mm outward. FIG. 5 is a section of the board 5 having first holes 71 for the outwardly bent first connecting pins 11 , and second holes 72 for the inwardly bent second connecting pins 12 . The first and second holes 71 and 72 are offset relative to each other by 1.27 mm. The spacing of the inline holes 71 and 72 is 2.54 mm. The spacing between two offset holes 71 and 72 is chosen as 1.8 mm. The connecting pins on the package may be arranged symmetrically relative to the longitudinal center axis and the transverse center axis of the package since this symmetrical arrangement allows for the use of a symmetrical bending tool. It is then irrelevant how the bending tool is placed on the package. It is impossible to bend the connecting pins incorrectly by attaching the bending tool with the improper orientation. The method according to the invention permits the use of packaging mechanisms suitable for the standard PSDIP package. No special packaging mechanisms are required. While the above figures describe an approach in which every second connecting pin is bent inward once, FIG. 6 illustrates another possibility. With this possibility, every second pin 12 is bent 90° downward, relative to the package. Every intermediate pin 11 , on the other hand, is first bent downward by less than 90° relative to the package, for example, by 45°, then subsequently bent by an additional angle, for example, 45°. Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
    同族专利
    暂无同族专利