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    一种稳定的螺内酯药物纳米粒组合物

    1107109885A
    发明人
    吴涛
    受让人
    BEIJING HUICHENG RUIXIANG PHARM BIOTECHN (BEIJ-Non-standard), BEIJING HUICHENG YIJIAN PHARM TECHNOLOGY (BEIJ-Non-standard)
    申请人
    Beijing Xiaomi Mobile Software Co. Ltd.
    申请号
    006339
    申请日
    1985-04-16
    公开(公告)号
    1107109885A
    公开(公告)日
    2014-02-06
    IPC分类号
    H01L027/00H01L021/31H01L021/00H01L021/469H01L051/40H05B033/10B05D007/00H05B033/12H05B033/14G09F009/00G09F009/30H05B033/22H05B033/00H01J009/00H01L033/00H01J001/62H01J063/04B05D001/36B05D001/38H01L029/08H01L021/208H01L051/56H01L027/32H01L051/50H01J001/63H01J009/26H01L023/58H01L051/52H01J009/24H01L051/00
    CPC分类号
    -
    优先权号
    1049129
    020792
    优先权日
    2001-10-04
    2002-09-16
    摘要

    An injection mold and process are arranged to produce very thin articles, such as data discs. Molten plastic is injected into mold parts forming a thin cavity (17), in a cyclic molding process wherein the mold parts are subjected to a substantially constant temperature stimulus and rise and fall in temperature during injection and cooling of the molten plastic. Temperature boosting thermal insulation layers (11, 21) are placed along at least certain parts of the molding cavity surface. This elevates the temperature of the molted melt material for a time during injection. According to a calculated relationship, this thermal insulation is sized to permit the thin mold cavity to fill before heat transfer to the mold parts solidifies the molding material and blocks further flow. The temperature boosters can be contoured in thickness.

    权利要求
    1.一种用于生成表示一个对象的内部的三维图像的系统，该系统包括：射线扫描器，该扫描器通过将射线穿过该对象传递到探测器上来生成投影信号；以及接收投影信号的计算机，用于通过对投影信号执行多种计算来生成三维图像，该计算机包括至少一个定点处理单元和至少一个浮点处理单元，该至少一个定点处理单元与该至少一个浮点处理单元并行操作，该计算机将该多种计算分为将在该至少一个定点处理单元中执行的第一组计算和将在该至少一个浮点处理单元中执行的第二组计算。
    2.根据权利要求1所述的系统，其中：所述第一组计算包括生成投影图；以及所述第二组计算包括根据投影图对锥形线束投影信号进行反投影，以便产生图像。
    3.根据权利要求2所述的系统，其中：生成投影图的过程包括将世界坐标系(x，y，z)映射到探测器的坐标系(u，t，s)，其中u独立于z；所述计算机将锥形线束投影信号组织为z行，其中z可以变化，但x和y保持恒定；以及该计算机为z行的每一个执行反投影。
    4.根据权利要求3所述的系统，其中，所述计算机进一步包括一个足够大而可以保存z行之一的高速缓存。
    5.根据权利要求3所述的系统，其中，在所述计算机为所有z行执行反投影以作为多个立体像素形成图像之后，该计算机对图像中的立体像素执行三维转置操作，以将该立体像素组织为x行，其中x可以变化，但y和z保持恒定。
    6.根据权利要求1所述的系统，其中：对象的一个边界已知是一个先验；以及三维图像只在该边界内生成。
    7.根据权利要求1所述的系统，其中，投影信号作为纯粹的浮点数据来处理。
    8.根据权利要求1所述的系统，其中，投影信号作为浮点和定点数据的混合来处理。
    9.根据权利要求1所述的系统，其中，所述计算机包括微处理器，在该微处理器上实现该至少一个定点处理单元和该至少一个浮点处理单元，该定点处理单元可在一个指令集内处理一个以上16位或32位整型数据，该浮点处理单元可在一个指令集内处理一个以上单精度32位浮点数据。
    10.根据权利要求9所述的系统，其中，所述计算机包括多个所述的微处理器，每一个微处理器包括至少一个所述的定点处理单元和至少一个所述的浮点处理单元，该定点处理单元可在一个指令集内处理一个以上16位或32位整型数据，该浮点处理单元可在一个指令集内处理一个以上单精度32位浮点数据。
    11.根据权利要求1所述的系统，其中，图像是所述对象的内部的线性衰减系数分布。
    12.根据权利要求1所述的系统，其中，辐射扫描器是一个辐射锥形线束扫描器，该辐线束是辐射锥形线束，且所述投影信号是锥形线束投影信号。
    13.一种用于生成表示一个对象的内部的三维图像的方法，该方法包括：(a)将线束穿过该对象传递到检测器上来生成投影信号；以及(b)接收投影信号并通过对锥形线束投影信号执行多种计算来生成三维图像；其中，步骤(b)是在计算机上执行的，该计算机包括至少一个定点处理单元和至少一个浮点处理单元，该至少一个定点处理单元与该至少一个浮点处理单元并行操作，该计算机将该多种计算分为将在该至少一个定点处理单元中执行的第一组计算和将在该至少一个浮点处理单元中执行的第二组计算。
    14.根据权利要求13所述的方法，其中：对象的一个边界已知是一个先验；以及三维图像只在该边界内生成。
    15.根据权利要求13所述的方法，其中，投影信号作为纯粹的浮点数据来处理。
    16.根据权利要求13所述的方法，其中，投影信号作为浮点和定点数据的混合来处理。
    17.根据权利要求13所述的方法，其中，所述计算机包括微处理器，在该微处理器上实现所述至少一个定点处理单元和所述至少一个浮点处理单元，该定点处理单元可在一个指令集内处理一个以上16位或32位整型数据，该浮点处理单元可在一个指令集内处理一个以上单精度32位浮点数据。
    18.根据权利要求17所述的方法，其中，所述计算机包括多个微处理器，每一个微处理器包括至少一个所述的定点处理单元和至少一个所述的浮点处理单元，该定点处理单元可在一个指令集内处理一个以上16位或32位整型数据，该浮点处理单元可在一个指令集内处理一个以上单精度32位浮点数据。
    19.根据权利要求13所述的方法，其中，所述图像是所述对象的内部的线性衰减系数分布。
    20.根据权利要求13所述的方法，其中，所述对象包括软组织。
    21.根据权利要求20所述的方法，其中，所述图像用于探测软组织中的癌。
    22.根据权利要求13所述的方法，其中，步骤(b)是使用人工编写的汇编语言执行的。
    23.根据权利要求13所述的方法，其中，步骤(b)是通过在单微处理器或多处理器上使用混合型计算进行并行处理来执行的，以便加速用于重建软组织的锥形线束重建。
    24.根据权利要求13所述的方法，其中，步骤(b)只有在多个处理器可用的情况下才通过多线程执行。
    25.根据权利要求13所述的方法，其中，所述线束是锥形线束，所述投影信号是锥形线束投影信号。
    26.根据权利要求25所述的方法，其中，步骤(b)是使用过滤的反投影锥形线束重建算法执行的。
    27.根据权利要求26所述的方法，其中，过滤的反投影锥形线束重建算法是使用采用了单指令多数据技术的混合型计算来执行的。
    28.根据权利要求27所述的方法，其中，过滤的反投影锥形线束重建算法是使用多线程在多个处理器上执行的。
    29.根据权利要求25所述的方法，其中，步骤(b)是通过费尔德坎普锥形线束重建算法执行的。
    30.根据权利要求25所述的方法，其中：所述第一组计算包括生成投影图；以及所述第二组计算包括根据投影图对锥形线束投影信号进行反投影，以便产生重建的图像。
    31.根据权利要求30所述的方法，其中：生成投影图的过程包括将世界坐标系(x，y，z)映射到探测器的坐标系(u，t，s)，其中u独立于z；所述计算机将锥形线束投影信号组织为z行，其中z可以变化，但x和y保持恒定；以及该计算机为z行的每一个执行反投影。
    32.根据权利要求31所述的方法，其中，所述计算机进一步包括一个足够大而可以保存z行之一的高速缓存。
    33.根据权利要求31所述的方法，其中，在所述计算机为所有z行执行反投影以作为多个立体像素形成图像之后，该计算机对该图像中的立体像素执行三维转置操作，以将该立体像素组织为x行，其中x可以变化，但y和z保持恒定。
    说明书
    [0001]CROSS REFERENCE TO RELATED APPLICATION This application is a divisional of application Ser. No. 10/485,139 filed Sep. 2, 2004 now U.S. Pat. No. 7,053,480 entitled “METHOD FOR TESTING A CHIP WITH A PACKAGE AND FOR MOUNTING THE PACKAGE ON A BOARD”.
    [0002]BACKGROUND OF THE INVENTION The invention relates to the field of semiconductor packaging and testing, and in particular to mounting an integrated circuit that has been tested on a board, wherein the adjacent connecting pins of the integrated circuit are in an inline arrangement. In order to keep the dimensions small for the package of a chip with multiple connecting pins (e.g., 88 pins), the connecting pins are arranged in line as close as possible. However, a minimum spacing must still be maintained since the space between associated holes on a board for insertion of the connecting pins may not be arbitrarily reduced. As the spacing of the holes and conducting lines on the board becomes closer, the process of fabricating a board becomes more complex and expensive. In addition, there is the risk that close spacing of the holes on the board will cause the connecting pins to short out during the soldering process. One technique for increasing hole spacing on the board is to configure the connecting pins of the package by bending some of the connecting pins or, for example, by inwardly offsetting every second connecting pin. However, the advantage of greater hole spacing on the board is counteracted by the disadvantages of requiring a special test socket to test the chips and requiring an expensive packaging mechanism. Specifically, the packaging mechanism must be designed such that the connecting pins are not bent out of their precise alignment. Therefore, there is a need for a method of testing and mounting the package on a board in such a way that simple and inexpensively produced test sockets are sufficient for testing, and similarly simple and inexpensively produced packaging mechanisms are sufficient for packaging, while at the same time achieving an offset arrangement for the connecting pins.
    [0003]SUMMARY OF THE INVENTION Briefly, according to an aspect of the invention, an integrated circuit that includes a die mounted within a package containing a plurality of input/output pins is tested by placing the integrated circuit into a test socket of automatic test equipment. Prior to the tested integrated circuit being mounted on a board, a portion of the plurality of input/output pins are bent from their inline position to an offset position. The integrated circuit with its inline connecting pins is inserted into a test socket for testing. At least one connecting pin is bent inward using a bending tool immediately before insertion of the connecting pins of the integrated circuit into the holes of the board, in order to achieve an offset arrangement of the connecting pins. The integrated circuit includes inline connecting pins (i.e., individuals skilled in the art frequently use the expression “dual inline”), and the integrated circuit is tested in this state. The integrated circuit to be tested is inserted into a test socket. A first advantage is that relatively inexpensive test sockets may be utilized to test the chips. A second advantage is that even inexpensive packaging mechanisms are sufficient for storing and transporting the chips. Additionally, at least one connecting pin, preferably every second connecting pin, is bent inward by the bending tool immediately before insertion of the connecting pins of the integrated circuit into the board in order to form an offset arrangement of the connecting pins. The invention thus combines the advantages of a package in which its connecting pins are in an inline arrangement with those of a package in which its connecting pins are in an offset arrangement. Electrical testing of the chip may thus be of a simple design since inexpensively produced test sockets are sufficient for the task. In addition, standard packaging mechanisms may be employed to package the package. Subsequent alignment of the connecting pins is simplified since the connecting pins are not bent into the offset arrangement until immediately before insertion into the board, rather than at the fabrication stage of the package. These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.
    [0004]BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a flowchart illustration of a method of testing an integrated circuit and bending selected external input/output pins of the integrated circuit and mounting the integrated circuit with selected external input/output pins bent an angle with respect to the inline position of the pins; FIGS. 1B-1F are simplified illustrations of the integrated circuit during the steps illustrated in FIG. 1A ; FIG. 2 is a top view illustration of an embodiment of a package with the bending tool attached; FIG. 3 is a front view illustration of the package of FIG. 2 with the bending tool attached; FIG. 4 is a front view illustration of an embodiment of a package; FIG. 5 is a section view of a board having holes for the connecting pins; and FIGS. 6A-6D illustrate another example of an integrated circuit.
    [0005]DETAILED DESCRIPTION OF THE INVENTION FIG. 1A is a flow chart illustration of a method 100 for testing an integrated circuit, bending the pins of the integrated circuit and mounting the integrated circuit. FIGS. 1B-1F are simplified sectional views of the integrated circuit during the steps illustrated in FIG. 1A . Referring to FIGS. 1A-1F , in step 102 inline connecting pins 1 of an integrated circuit that includes a die (not shown) and a package 2 containing the die, are input to a test socket 3 as shown in FIG. 1B . In step 104 , any rework that may be required on the package 2 or the chip is performed. The package 2 is then placed in a packaging mechanism such as a guide brace 4 and shipped in step 106 . Immediately before the package 2 is mounted on a board 5 , every second connecting pin 12 , for example, is bent inward by a bending tool 6 , while the remaining connecting pins 11 are left unmodified. The connecting pins 11 and 12 are inserted into associated holes 71 - 72 of the board 5 , preferably, by the bending tool 6 . FIG. 2 is a top view illustration of the package 2 , along with the connecting pins 11 and 12 , and with the bending tool 6 attached. FIG. 3 is a front view illustration of the package 2 with the connecting pins 11 and 12 , and with the bending tool 6 attached. Every second connecting pin 12 is bent inward, while the remaining connecting pins 11 remain bent outward or are oriented vertically, as is the case during fabrication of the package 2 . FIG. 4 is a front view of the package 2 , with the first connecting pins 11 bent outward and the second connecting pins 12 bent inward, including dimensional details. The spacing between the vertical pins on the package is 19.05 mm. The second connecting pins 12 are bent 0.4 mm inward from the vertical, while the first or remaining connecting pins 11 are bent 0.87 mm outward. FIG. 5 is a section of the board 5 having first holes 71 for the outwardly bent first connecting pins 11 , and second holes 72 for the inwardly bent second connecting pins 12 . The first and second holes 71 and 72 are offset relative to each other by 1.27 mm. The spacing of the inline holes 71 and 72 is 2.54 mm. The spacing between two offset holes 71 and 72 is chosen as 1.8 mm. The connecting pins on the package may be arranged symmetrically relative to the longitudinal center axis and the transverse center axis of the package since this symmetrical arrangement allows for the use of a symmetrical bending tool. It is then irrelevant how the bending tool is placed on the package. It is impossible to bend the connecting pins incorrectly by attaching the bending tool with the improper orientation. The method according to the invention permits the use of packaging mechanisms suitable for the standard PSDIP package. No special packaging mechanisms are required. While the above figures describe an approach in which every second connecting pin is bent inward once, FIG. 6 illustrates another possibility. With this possibility, every second pin 12 is bent 90° downward, relative to the package. Every intermediate pin 11 , on the other hand, is first bent downward by less than 90° relative to the package, for example, by 45°, then subsequently bent by an additional angle, for example, 45°. Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
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