The growing demand for long-context LLM inference has exposed a critical bandwidth–capacity trade-off in memory systems, rendering single-tier PIM architectures ineffective. HBM-PIMs offer high bandwidth but limited capacity, while DIMM-PIMs provide scalability at the cost of lower bandwidth; neither satisfies the throughput-latency requirements of long-context serving workloads for LLMs. To address this, we propose HydraPIM, a heterogeneous multitier PIM architecture that decomposes attention computation across HBM-PIM and DIMM-PIM tiers by exploiting the inherent sparsity of attention. HydraPIM introduces HydraAttention, a tiled attention mechanism with hierarchical reduction, enabling efficient cross-tier execution through lightweight on-chip reduction units. To maintain load balance under dynamic access patterns of sparse attention, HydraPIM features an importanceaware KV migration mechanism that monitors token relevance and relocates hot tokens to high-bandwidth tiers at runtime. This software-hardware co-design helps improve the utilization of both bandwidth and capacity. Evaluations show that HydraPIM achieves 1.66× higher throughput than HBM-based NPU-PIM and 1.96× lower latency than DIMM-based NPU-PIM across diverse long-context workloads.

Numerous quantum algorithms assume that classical data has already been converted into quantum states, a process known as Quantum State Preparation (QSP). However, achieving precise QSP requires a circuit depth that scales exponentially with the number of qubits, posing a significant challenge to realizing quantum advantage. Recent research explores Parameterized Quantum Circuits (PQCs) as an approximate alternative, offering improved scalability with reduced circuit depth. However, the iterative, state-by-state optimization required by this approach creates substantial runtime overhead, which severely limits its practicality. To improve the efficiency of approximate QSP, we introduce a novel two-stage framework that can potentially generate QSP circuits for arbitrary quantum states. In the offline training stage, our model learns a direct mapping from target states to circuit parameters, thereby bypassing the need for online, state-by-state optimization during the inference stage. Extensive evaluations show that our approach significantly reduces runtime overhead by up to 132x, making a steady step towards efficient neural approximate QSP.

Multi-modal Retrieval-Augmented Generation (RAG) has emerged as a highly effective paradigm for Knowledge-Based Visual Question Answering (KB-VQA). Despite recent advancements, prevailing methods still primarily depend on images as the retrieval key, and often overlook or misplace the role of Vision-Language Models (VLMs), thereby failing to leverage their potential fully. In this paper, we introduce WikiSeeker, a novel multi-modal RAG framework that bridges these gaps by proposing a multi-modal retriever and redefining the role of VLMs. Rather than serving merely as answer generators, we assign VLMs two specialized agents: a Refiner and an Inspector. The Refiner utilizes the capability of VLMs to rewrite the textual query according to the input image, significantly improving the performance of the multimodal retriever. The Inspector facilitates a decoupled generation strategy by selectively routing reliable retrieved context to another LLM for answer generation, while relying on the VLM's internal knowledge when retrieval is unreliable. Extensive experiments on EVQA, InfoSeek, and M2KR demonstrate that WikiSeeker achieves state-of-the-art performance, with substantial improvements in both retrieval accuracy and answer quality. Our code will be released on https://github.com/zhuyjan/WikiSeeker.

Wafer-scale chips (WSCs) like the Cerebras WaferScale Engines (WSEs) offer immense on-chip compute and bandwidth for large-scale Artificial Intelligence (AI) workloads, but their massive area makes defect-free fabrication impossible, posing severe yield and cost challenges. The traditional solution is chip binning, which grades chips by frequency or core count, but such metrics fail for WSCs as their performance is not only determined by core number but also heavily influenced by the communication irregularities caused by faults. These fault-induced variations cause large inter-chip performance divergence, forcing conservative binning thresholds that reduce premium-bin yield (i.e. the fraction of chips in the highest-performance bins) and the aggregate guaranteed performance delivered across bins (i.e., the total sellable effective compute capacity, SECC). Therefore, a new binning strategy and performance-convergence mechanisms are essential for the practical commercialization of WSCs. To address these challenges, we first propose Performance Binning, a novel paradigm that grades WSCs by their actual performance on target workloads rather than by core count or frequency. We further develop a Performance-Convergence Framework for WSC Binning (ConBIN) that unifies hardware design, software optimization, and performance binning to converge the inter-chip performance distribution and maximize binning yield. ConBIN employs automated, fault-correlationaware redundant interconnect design and post-silicon fault repair to reduce inter-chip divergence of core counts and topology structures. It then applies bin-aware workload mapping and finegrained communication scheduling guided by lightweight prebinning targets to suppress residual performance variance, which enables tighter chip bin thresholds and higher premium-bin yield, boosting overall SECC. Finally, ConBIN executes performance binning to determine binning thresholds that maximize total SECC. Evaluations show that ConBIN improves premium-bin yield by 2.80× and total SECC by 2.64× over state-of-the-art (SOTA) fault-tolerant methods on $\mathbf{1 2 8} \times \mathbf{1 3 6}$ WSCs.

In multi-chiplet systems, inter-chiplet shared-data transfers pose a significant bottleneck, prolonging the critical paths of memory accesses. In inter-chiplet coherence traffic, since each chiplet often needs to wait reactively for data from remote chiplets, proactive data-fetching mechanisms such as prefetching are essential to anticipate inter-chiplet data accesses and mitigate latency. Nevertheless, traditional prefetchers are inadequate for explicitly handling inter-chiplet shared-data transfers, overlooking potential prefetching opportunities. To overcome this limitation, we propose SAP, a shared-aware prefetching mechanism that minimizes inter-chiplet data access latency. By transforming the IO chiplet into an active prefetching agent, SAP proactively fetches inter-chiplet shared data before demand requests arrive, utilizing a sharing table to track recent shared-data events and a prefetch agent to initiate inter-chiplet data transfers early. Our experiments on a chiplet-based system demonstrate that SAP improves system throughput by 13.44% and reduces execution time by 12.33% compared to the prior design.

The spatiotemporal evolution of a single physical element in oceanic data analysis is often closely related to multiple other climatic elements. However, the coupling relationships between physical elements are highly nonlinear, making it difficult to accurately predict future changes through a limited set of physical equations. Established on multimodal data analysis, this paper proposes a data-driven spatiotemporal prediction model (AtmosOceanNet) to help simulate the nonlinear coupling relationships among various elements in ocean and atmosphere systems. The model has integrated an orchestrated set of advanced features in artificial intelligence: UNet, temporal-spatial (TS) conversion, multimodality, attention mechanism, and diffusion module. The encoder-decoder structure of UNet serves as the backbone. The TS Conversion is the input-output module of the model, which creatively endows spatial analysis models with the capability to analyze temporal characteristics. A similarity attention mechanism is proposed, enabling the model to automatically retrieve spatiotemporal evolution from multimodal data. A Diffusion Model (DM) branch is introduced to model uncertainties from a probabilistic distribution perspective, which are often exhibited by natural spatiotemporal sequences. To validate our model’s predictive capabilities for spatiotemporal sequences, experiments of Sea Surface Temperature (SST) prediction are conducted. The area covers the entire Asia Pacific Sea (APS). Results indicate that multiple modalities can greatly enhance the performance. Compared to state-of-the-art spatiotemporal prediction methods, our model demonstrated an up to 13% improvement for the next 7 days. Code will be available at https://github.com/xuanxuan4AI/AtmosOceanNet

Infrared radiation computing underpins advances in climate science, remote sensing and spectroscopy but remains constrained by manual workflows. We introduce InfEngine, an autonomous intelligent computational engine designed to drive a paradigm shift from human-led orchestration to collaborative automation. It integrates four specialized agents through two core innovations: self-verification, enabled by joint solver-evaluator debugging, improves functional correctness and scientific plausibility; self-optimization, realized via evolutionary algorithms with self-discovered fitness functions, facilitates autonomous performance optimization. Evaluated on InfBench with 200 infrared-specific tasks and powered by InfTools with 270 curated tools, InfEngine achieves a 92.7

To exploit apabilities of processors in contemporary heterogeneous systems, frequent data movement across disparate memory domains is required. The substantial overhead incurred by this data transfer is now a principal bottleneck for system performance, especially for computationally intensive, large-scale AI workloads. To address this, we propose CGR-NPU, a hybrid architecture that synergistically combines a Coarse-Grained Reconfigurable Array (CGRA) with a Neural Processing Unit (NPU). The architecture features tightly-coupled CGRA and NPU operational modes with fast switching, and leverages a reinforcement learning-based mechanism for dynamic resource allocation tailored to workload characteristics. Evaluations on diverse ML benchmarks show our integrated architecture improves average 1.62 & times; performance speed up and reduces silicon area by 48.4% compared to standalone CGRA or NPU baselines. The overhead for mode switching and internal data handling is minimal, constituting only 7% of the total execution time.

Accurate extraction of rural roads from high-resolution remote sensing imagery is essential for infrastructure planning and sustainable development. However, this task presents unique challenges in rural settings due to several factors. These include high intra-class variability and low inter-class separability from diverse surface materials, frequent vegetation occlusions that disrupt spatial continuity, and narrow road widths that exacerbate detection difficulties. Existing methods, primarily optimized for structured urban environments, often underperform in these scenarios as they overlook such distinctive characteristics. To address these challenges, we propose DSFC-Net, a dual-encoder framework that synergistically fuses spatial and frequency-domain information. Specifically, a CNN branch is employed to capture fine-grained local road boundaries and short-range continuity, while a novel Spatial-Frequency Hybrid Transformer (SFT) is introduced to robustly model global topological dependencies against vegetation occlusions. Distinct from standard attention mechanisms that suffer from frequency bias, the SFT incorporates a Cross-Frequency Interaction Attention (CFIA) module that explicitly decouples high- and low-frequency information via a Laplacian Pyramid strategy. This design enables the dynamic interaction between spatial details and frequency-aware global contexts, effectively preserving the connectivity of narrow roads. Furthermore, a Channel Feature Fusion Module (CFFM) is proposed to bridge the two branches by adaptively recalibrating channel-wise feature responses, seamlessly integrating local textures with global semantics for accurate segmentation. Comprehensive experiments on the WHU-RuR+, DeepGlobe, and Massachusetts datasets validate the superiority of DSFC-Net over state-of-the-art approaches.

Heterogeneous architectures that combine neural processing unit (NPU) and processing-in-memory (PIM) are increasingly adopted to accelerate LLM inference. Prior work focuses on building a unified memory that allows NPUs and PIM to share data without duplication. However, these designs implicitly assume that each tensor is bound to a fixed execution device, and therefore rely on static, device-biased data mappings. We observe that this assumption does not hold in modern LLM workloads. Due to phase changes (e.g., prefill vs. decode) and dynamic behaviors such as MoE routing, the optimal execution device for the same tensor can change at runtime. Under such dynamic execution, device-biased mappings become mismatched to access patterns, leading to substantial bandwidth underutilization and performance loss. This paper presents PFM (PIM-as-Flexible-Memory), a dual-view memory system that decouples physical data layout from accessor-visible logical views. PFM stores data in a jointly optimized physical layout and exposes different logical interpretations to NPUs and PIM, enabling efficient access across devices without data duplication or relayout. We further design accessor-aware address translation and runtime scheduling mechanisms to support dynamic execution when LLM workloads fluctuate and the optimal execution device dynamically changes. Our evaluation across LLMs shows that PFM improves end-to-end throughput by up to 2.32×, demonstrating its effectiveness and broad applicability as a unified memory management solution for NPU-PIM systems.

Quantum compilation reconciles a program's idealized interaction topology with hardware locality constraints, yet evaluations at scale lack calibrated references for realization overhead. We present QROB, a scalable reverse-construction methodology that generates compilation instances backward from directly realizable configurations, retaining the inverse paths as feasible, compiler-independent references. QROB provides a common evaluation substrate for NISQ SWAP routing and fault-tolerant lattice-surgery scheduling, while extending its reference-preserving principle to capacity-constrained quantum memory-access scheduling. Across systems ranging from 9 to 156 qubits, evaluations highlight QROB's utility as both a diagnostic benchmark and a data source. First, for compiler characterization, QROB reveals substantial realization gaps in existing tools, with NISQ compilers incurring up to 24.1x the reference SWAP cost and fault-tolerant compilers requiring up to 7.0x the reference makespan. Second, as a supervision source for data-driven compilation, a router trained on QROB references outperforms Qiskit SABRE on 84.8

The decomposition-based chiplet design paradigm, which breaks monolithic system-on-chips (SoCs) into smaller chiplets, has proved effective in reducing costs and accelerating development. The vast design space of multichiplet systems necessitates automated techniques to maximize their benefits while minimizing overheads. However, current chiplet decomposition flows lack support for exploring reusable chiplets, missing opportunities to efficiently amortize nonrecurring engineering (NRE) costs. To fully unleash the economic potential of chiplets, we propose Chipletizer 2.0, a cost-driven framework that guides SoC decomposition and enables chiplet reuse across a line of products. This early-stage chiplet planning framework determines critical system parameters involving the partition, floorplan, and die-to-die (D2D) interface, based on user-specified optimization goals. Experimental results demonstrate that, compared with the existing chiplet decomposition techniques, our proposed framework achieves significant cost improvements on realistic product lines with acceptable overheads.

Multimodal Large Language Models (MLLMs) demonstrate impressive cross-modal capabilities, yet their substantial size poses significant deployment challenges. Knowledge distillation (KD) is a promising solution for compressing these models, but existing methods primarily rely on static next-token alignment, neglecting the dynamic token interactions, which embed essential capabilities for multimodal understanding and generation. To this end, we introduce , a novel KD framework designed from the perspective of oken nteractions. Our approach is motivated by the insight that MLLMs rely on two primary interactions: vision-instruction token interactions to extract relevant visual information, and intra-response token interactions for coherent generation. Accordingly, Align-TI introduces two components: IVA enables the student model to imitate the teacher's instruction-relevant visual information extract capability by aligning on salient visual regions. TPA captures the teacher's dynamic generative logic by aligning the sequential token-to-token transition probabilities. Extensive experiments demonstrate Align-TI's superiority. Notably, our approach achieves 2.6% relative improvement over Vanilla KD, and our distilled Align-TI-2B even outperforms LLaVA-1.5-7B (a much larger MLLM) by 7.0%, establishing a new state-of-the-art distillation framework for training parameter-efficient MLLMs.

Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly to annotate. Existing work therefore focuses on small-scale circuits with clean labels, limiting scalability to realistic designs. Meanwhile, Large Language Models (LLMs) can generate Register-Transfer-Level (RTL) at scale, but their functional incorrectness has hindered their use in circuit analysis. In this work, we make a key observation: even when LLM-Generated RTL is functionally imperfect, the synthesized netlists still preserve structural patterns that are strongly indicative of the intended functionality. Building on this insight, we propose a cost-effective data augmentation and training framework that systematically exploits imperfect LLM-Generated RTL as training data for netlist representation learning, forming an end-to-end pipeline from automated code generation to downstream tasks. We conduct evaluations on circuit functional understanding tasks, including sub-circuit boundary identification and component classification, across benchmarks of increasing scales, extending the task scope from operator-level to IP-level. The evaluations demonstrate that models trained on our noisy synthetic corpus generalize well to real-world netlists, matching or even surpassing methods trained on scarce high-quality data and effectively breaking the data bottleneck in circuit representation learning.

Conventional LLM inference architectures suffer from high energy and latency due to frequent data movement across memory hierarchies. We propose Ouroboros, a wafer-scale SRAM-based Computing-in-Memory (CIM) architecture that executes all operations in situ, eliminating off-chip migration. To maximize its limited first-level capacity, we introduce three innovations: Token-Grained Pipelining: Replaces sequence-level pipelining to mitigate length variations, boosting utilization and reducing activation storage. Distributed Dynamic KV Cache Management: Decouples memory from compute to leverage fragmented SRAM for efficient KV storage. Communication-Aware Mapping: Optimizes core allocation for locality and fault tolerance across the wafer. Experimental results show Ouroboros achieves average gains of 4.1× in throughput and 4.2× in energy efficiency, peaking at 9.1× and 17× for the 13B model. (*Due to the notification of arXiv "The Abstract field cannot be longer than 1,920 characters", the appeared Abstract is shortened. For the full Abstract, please download the Article.)

This paper investigates the identification problem for finite impulse response (FIR) systems with binary-valued observations under event-triggered communication mechanism and data packet dropout. The challenge lies in the inability to distinguish between untriggered events and packet loss when no information is received, which prevents us from obtaining the statistical properties of the binary-valued sequence. A compensation-oriented difference-driven identification (CODD) algorithm is proposed to estimate the parameter by recovering the mean of the original binary-valued sequence, where different values for the observation estimates are assigned when receiving 0, 1 or nothing. Even though, the convergence analysis of the parameter estimate is still challenging since the assigned values are dependent. To tackle this difficulty, the estimate error is divided into two parts: an initial assigned value related part, which is demonstrated to be convergent through the construction of an auxiliary set, and the remaining component, which happens to be a convergent martingale-difference sequence. As a result, the almost sure convergence and the asymptotic normality of the CODD algorithm are established when data packet loss probability is less than 21. By calculating the communication rate, it is proven that the difference-driven mechanism can save 50% of the communication cost compared to original binary-valued systems. Furthermore, when data packet loss probability is high, an m-channel compensation-oriented identification (m-CODD) algorithm is constructed by utilizing retransmission of the each observation for m times, which is designed based on the packet loss probability. The properties of m-CODD algorithm including convergence, asymptotic normality and communication rate are established. Numerical simulations are illustrated to show the theoretical results. (c) 2025 Published by Elsevier Ltd.