This work focuses on implementing You Look Only Once (YOLO) models on resource-constraint devices with improved generalization, for drone imagery-based multi-object detection. The generalization improvement has been done using a proposed meta-training framework. The proposed meta-training is an aspect of transfer learning that focuses on domain generalization (or adaptation) through learning a variety of domains using transfer learning. Herein, different domains have distinct tasks with adversaries such as object detection in the nighttime, crowds, sunny weather, and small object areas, the model is learning to adapt to the next domain iteratively through a gradient descent-based optimization. Three different configurations of YOLO, publicly available data, and custom-made data are involved in validating the improved generalization. Each model has been trained on a big fraction of both datasets one by one, and predictions have been taken within both datasets. The average precision (AP) values and other visual results have been calculated in various cases to demonstrate enhanced multi-object detection. Furthermore, the model has been deployed on three commercially available resource-constrained devices. The related codes are available on GitHub: https://github.com/vy0123/Yolov8_drone_vision.git.

Human Activity Recognition (HAR) is a significant field within human-computer interaction, often utilizing deep learning (DL) techniques for improved performance. However, DL's resource-intensive nature poses challenges, especially on memory-limited devices like smartphones and other edge devices. To address this issue, we propose a novel approach combining Wavelet Transform (WT) and DL. By decomposing smartphone signals using WT and feeding them into a Multiscale Convolutional Neural Network (MSCNN), our method effectively extracts features at different scales for adaptive HAR without the need for manual feature extraction. This WT-MSCNN model offers advantages in processing non-stationary data, extracting HAR information effectively, and maintaining robustness to scale uncertainties in signals. Our experimental results indicate that the proposed methodology attains an accuracy of 98%, a sensitivity of 99%, a specificity of 97%, and an F1-score of 98.10% on NVIDIA Tesla T4 GPU (Graphics Processing Unit). Additionally, our model has demonstrated enhanced throughput, outperforming fine-tuned MobileNet-V3 and SqueezeNet Models by 83.59% and 25.72% respectively on the Raspberry Pi 4 hardware platform.

Neural network architectures are increasingly pop-ular for their ability to perform fast and efficient compu-tations, leveraging inherent parallelism for quicker operation than conventional sequential methods. This paper presents a novel reconfigurable neural network architecture implemented with computationally less intensive hardware, along with a hardware accelerator-based design of a feed-forward neural network. The primary aim of this work is to optimize power and area utilization metrics using an approximate computing paradigm and a control unit that synchronizes the forward and backward passes. Moreover, in this paper, we introduce a compact and scalable hardware design approach for neural networks, validated through simulations and implementations on Xilinx Zynq and Zynq UltraScale+ MPSoC FPGA boards. Our architecture significantly reduces area overhead by 2.58 %, enhances power efficiency with an average power consumption of 110.67 mW, and achieves a 4.68-fold increase in throughput compared to software implementations. This improvement, while maintaining an average accuracy of around 91 % across different architectures, is due to the use of reconfigurable features and Padé-based optimization techniques.

With the extensive use of surveillance-based systems in the present age, it is recommended to employ lightweight deep neural networks (DNNs) that not only have small silicon footprints and low latency but also provide enhanced security. In this paper, we incorporate a lightweight Attention-CNN algorithm on drones for image classification in smart city surveillance systems. By processing data directly on the drone, our approach significantly reduces the delay associated with data transmission to centralized servers, enhancing the effectiveness of surveillance operations. We ensure that our algorithms maintain high accuracy while operating within the constraints of the hardware resources. Additionally, we evaluate the resilience of these DL models against adversarial attacks, considering the security implications of deploying in real-life applications. To address the demands of latency-sensitive applications that require rapid analysis of high-resolution images, we also explore the implementation on a field-programmable gate array board. The experimental results show a maximum reduction factor of 9.56 in the memory size along with a 2.92% drop in the accuracy in the software implementation and the total power consumption on the ZCU104 FPGA board is 10 W.

Implementation of deep learning models is constrained by different memory and computational requirements. While significant progress has been made in enhancing the processing element performance, the complete system throughput largely depends on memory transfer from the off-chip interfaces. This work proposes a complete on-chip solution for accelerator implementation on devices with resource constraints. We propose batch-wise clustering of the weights of DL models and in-situ generation of weights to be fed to the acceleration for the computations as per the model specifications. This architectural change is further complemented by the popular technique of zero-skipping. Experimental observations indicate that an average reduction in model parameters of more than 26% can be obtained at a 10% reduction in accuracy for three benchmark models extensively used in the literature.

Smart wearable devices benefit from lightweight deep neural networks (DNNs) with small silicon footprints for efficient real-time processing. While compression techniques are often applied to heavier models, achieving lightweight DNNs for wearable technology, particularly in real-time applications, has been underexplored. This work proposes a knowledge-distillation approach to derive a lightweight student model from a pre-trained teacher model, which maintains high performance. Tested on real-world ECG data, the student DNN achieves 89% classification accuracy, matching the teacher model, with a 93.12% memory reduction. Furthermore, deployment on resource-constrained devices like Coral TPU shows a 2 to 6.5-fold throughput improvement compared to other devices.

There is a growing interest in using Deep learning (DL) to analyse sensor data for monitoring heart-rate, aiming for earlier and accurate prediction of cardiovascular diseases (CvD). However, the resource-intensive nature of DL pose challenges, particularly on memory-limited devices like smartphones and other edge devices. To address this issue, we propose a novel approach that combines a Convolutional Neural Network-Hidden Markov Model (CNN-HMM). In this model, features from signals on smartphones or other edge devices are extracted using a CNN block, while classification is performed using an HMM. This CNN-HMM model offers advantages in processing non-stationary data and effectively extracting heart rate information. Additionally, we aim to address the challenge of Deep Neural Network (DNN) inference on resource-constrained edge devices by systematically comparing different light-weight models on several commercial hardware platforms (Raspberry Pi 4, high-performance computing (HPC) platforms) across popular frameworks, highlighting their performance and limitations. The proposed approach has achieved an accuracy of 96.39%, a precision of 96.27%, a recall of 97.20%, and an F1-score of 96.73% on NVIDIA Tesla T4 GPU (Graphics Processing Unit). Additionally, our model has demonstrated enhanced throughput, outperforming fine-tuned MobileNetV2, NASNet-Mobile, and MobileNetV3Small models by 77.62%, 138.65%, and 39.92% respectively on the Raspberry Pi 4 hardware platform.

Generative Adversarial Networks (GANs) have achieved remarkable success in producing high-quality images. However, their deployment on resource-constrained devices, such as edge devices, is challenging due to heavy computational requirements and substantial memory usage. Despite recent advancements in compressing GANs, there is still room for further optimization, as existing methods may introduce potential model redundancies. To address this issue, we explore various optimization techniques, including Knowledge Distillation, Quantization-Aware Training, and Post-training quantization, aiming to create lightweight GANs that can generate high-fidelity images with reduced computational demands. Our experimental results on two benchmark datasets showcase significant compression achievements, with a $70.31 \%$ reduction in model size for Cycle GAN and a $\mathbf{7 5. 4 1 \%}$ reduction for Neural Style Transfer GAN, all while maintaining image quality.

The generation of vast amounts of data, coupled with significant advancements in computational platforms, offers numerous opportunities for a wide range of classification tasks across various applications. These classifications have been made possible by successful research in deep learning (DL) methodologies over the past decade, which have progressively matured and achieved human-level accuracy. Healthcare applications are a major segment where DL algorithms with transfer learning have tremendous opportunities for different tasks viz. test diagnosis, prognosis, and treatment strategies. In this paper transfer learning-assisted deep neural network design and Deep Learning Processor Unit-based hardware implementation for multiple healthcare applications is presented. Experimental results indicate that the proposed methodology can enable different state-of-the-art model implementations to achieve significant accuracies of 95.2%, 98.5%, and 98.2%, and frame rates of 498.24, 546.89, and 368.24 FPS (frames per second) on different benchmark datasets.

Deep learning accelerators play a crucial role in accelerating the performance of deep neural networks. As these accelerators become more complex, ensuring their correctness and reliability becomes increasingly challenging. Formal verification techniques offer a systematic approach to rigorously validate the design and verify its functional correctness. In this case study, we present a detailed analysis of verifying an open-source deep learning accelerator design (at RTL abstraction), highlighting the methodology, challenges, steps and outcomes of an enhanced formal verification process.

Recent technological advancements enabled integration of a wide variety of Intellectual Property (IP) cores in a single chip, popularly known as System-on-a-Chip (SoC). Network-on-Chip (NoC) is a scalable solution that enables communication between a large number of IP cores in modern SoC designs. A typical SoC design methodology relies on third-party IPs to reduce cost and meet time-to-market constraints, leading to serious security concerns. NoC becomes an ideal target for attackers due to its distributed nature across the chip as well as its inherent ability in monitoring communications between the individual IP cores. This paper presents a comprehensive NoC trust validation framework using security assertions. It makes three important contributions. (1) We define a set of security vulnerabilities for NoC architectures, and propose security assertions to monitor these pre-silicon vulnerabilities. (2) In order to ensure that the generated assertions are valid, we utilize efficient test generation techniques to activate these security assertions. (3) We develop on-chip triggers based on synthesized security assertions as well as efficient security-aware signal selection techniques for effective post-silicon debug. Experimental results show that our proposed framework is scalable and effective in capturing security vulnerabilities as well as functional bugs with minor hardware overhead.

Hardware accelerators have gained immense popularity in recent times for a varied range of healthcare applications. With the growth of edge computing, a large number of sensors can be integrated to enable lightweight computing for processing information. Over the years, there has been significant improvement in deep learning algorithms that offer exciting opportunities for their deployment even in safety-critical biomedical and healthcare applications. A detailed review and discussion on multiple challenges in the design of hardware acceleration catering to healthcare applications are presented in this paper. A wide range of generalized novel architectures and devices offers certain distinct advantages over the conventional processing units. Despite this development, the power and resource constraints of these platforms create significant hindrances in the acceleration of these high-risk medical applications. An elaborate analysis of the range of solutions to overcome these obstacles as well as a perspective on the need to address reliability and security concerns are presented. An alternative correct-by-construction accelerator design methodology is also proposed.

Edge computing allows the analysis of data close to the sources of its generation. This computing paradigm has enabled multiple avenues in different types of applications with the usage of Artificial Intelligence. Smart remote health monitoring is one such application that requires medical data analysis with the help of AI. In this paper, a methodology for blood pressure estimation from Electrocardiograph data using Machine Learning (ML) techniques is proposed that can be run on resource-constrained devices e.g., wearable devices. The proposed methodology requires only ECG data that can be acquired in a non-invasive manner. Experimental results show that the proposed methodology is able to achieve better results compared to similar techniques proposed in the literature.

Manufacturing of integrated circuits at the smaller technology nodes leads to several defects in them that must be screened and appropriately diagnosed for minimization of cost overruns. A substantial portion of the functional failures during the process of manufacturing test is often attributed to the defects inside the scan chains. With the advancements in the digital test technologies, almost every chip is manufactured with in-built pattern compression infrastructure. This exacerbates the problem of scan chain diagnosis from the collected failure traces. In this work, an automated methodology to perform this diagnosis in the presence of multiple faults is proposed. Deep learning is utilized to predict the probable candidate locations given the compressed scan chain response. Experiments have been performed on different fault models. Experimental results indicate that the proposed methodology is able to perform the diagnosis with a success rate of approximately 80-100%.

Effective bug localization during verification is a challenging step in the development cycle of complex hardware designs. While meeting different coverage goals is possible in the verification process, yet bug localization cannot be directly related to such goals. We propose a two-step methodology to achieve fine-grained design bug localization. First, we obtain multiple error traces based on a failing property. Starting from an initial error trace, we employ model checking to generate supportive error traces that are utilized to mine important assertions. In the second step, we utilize these assertions for fine-grained design bug localization. The mapping of the assertions leads to specific regions in register transfer level descriptions that are highly probable to be the root cause of the design bug. Specifically, we devise a binning methodology to categorize multiple suspects in different bins that need to be investigated by the design engineer for arriving at the correction for corresponding bugs. Experiments on multiple designs illustrate the efficacy of the proposed methodology in comparison to previous work and state-of-the-art industrial tool.

Generating quality testbenches during the verification of hardware designs is a highly challenging task. High quality testbenches with appropriate constraints assist in enhancing verification runs leading to quick debug. However, for the purpose of obtaining meaningful constraints in the testbench, a systematic methodology is needed. We propose Genetic Algorithm-based methodology for obtaining testbenches directed towards bug localization. The proposed methodology utilizes coverage metrics for providing feedback to the testbench enhancement process. We perform detailed case studies on two designs to evaluate the proposed methodology. Experimental results illustrate that with the generated constraints, a directed testbench can be crafted for exposing the design bug.

Design debugging is one of the most important steps in the modern integrated circuits (ICs) development cycle. Simulation-based verification is never sufficient for ensuring design correctness because of its incomplete nature. Formal techniques such as model checking promise to solve this issue through a complete state-space traversal approach. However, because of increasing design complexity, such methods suffer from scalability issues. Guidance-based state-space traversal techniques have been proposed in the past to assist the model checkers in overcoming the complexity bottleneck. Automatically identifying these guidance hints is relatively difficult and requires heuristic-based reasoning procedures. Additionally, to come up with quick fixes during the debug stage, an effective bug localization strategy is needed. In this article, we revisit the paradigm of guidance-based model checking and propose a methodology to improve these guidance generation mechanisms for achieving fine-grained bug localization. In particular, this work proposes a systematic methodology to localize the buggy RTL lines from the erroneous RTL simulation trace. The proposed technique involves the mining of invariant-like assertions from simulation traces. The mined assertions act as probable guidance candidates for the model checking exercise. To identify useful guidance hints from possible ones, we use the Bayesian networks that explore conditional dependence between the various hints at different levels and the target property. These guidance hints are utilized for obtaining possible buggy subregions, which are analyzed via an iterative model checking methodology for fine-grained bug localization. By using the proposed framework, bugs can be localized to within a few lines of RTL description.

The remarkable predictive performance of deep neural networks (DNNs) has led to their adoption in service domains of unprecedented scale and scope. However, the widespread adoption and growing commercialization of DNNs have underscored the importance of intellectual property (IP) protection. Devising techniques to ensure IP protection has become necessary due to the increasing trend of outsourcing the DNN computations on the untrusted accelerators in cloud-based services. The design methodologies and hyper-parameters of DNNs are crucial information, and leaking them may cause massive economic loss to the organization. Furthermore, the knowledge of DNN's architecture can increase the success probability of an adversarial attack where an adversary perturbs the inputs and alter the prediction. In this work, we devise a two-stage attack methodology "DeepPeep" which exploits the distinctive characteristics of design methodologies to reverse-engineer the architecture of building blocks in compact DNNs. We show the efficacy of "DeepPeep" on P100 and P4000 GPUs. Additionally, we propose intelligent design maneuvering strategies for thwarting IP theft through the DeepPeep attack and proposed "Secure MobileNet-V1". Interestingly, compared to vanilla MobileNet-V1, secure MobileNet-V1 provides a significant reduction in inference latency ($\approx$60%) and improvement in predictive performance ($\approx$2%) with very-low memory and computation overheads.

The remarkable predictive performance of deep neural networks (DNNs) has led to their adoption in service domains of unprecedented scale and scope. However, the widespread adoption and growing commercialization of DNNs have underscored the importance of intellectual property (IP) protection. Devising techniques to ensure IP protection has become necessary due to the increasing trend of outsourcing the DNN computations on the untrusted accelerators in cloud-based services. The design methodologies and hyper-parameters of DNNs are crucial information, and leaking them may cause massive economic loss to the organization. Furthermore, the knowledge of DNN’s architecture can increase the success probability of an adversarial attack where an adversary perturbs the inputs and alters the prediction. In this work, we devise a two-stage attack methodology “DeepPeep,” which exploits the distinctive characteristics of design methodologies to reverse-engineer the architecture of building blocks in compact DNNs. We show the efficacy of “DeepPeep” on P100 and P4000 GPUs. Additionally, we propose intelligent design maneuvering strategies for thwarting IP theft through the DeepPeep attack and proposed “Secure MobileNet-V1.” Interestingly , compared to vanilla MobileNet-V1, secure MobileNet-V1 provides a significant reduction in inference latency (≈60%) and improvement in predictive performance (≈2%) with very low memory and computation overheads.

Security concerns are growing rapidly in the modern age of the widespread use of electronic products. Due to the increasing dependability on integrated circuits like processors, a security attack can lead to massive damages in different forms. Apart from software-based attacks, design errors in the hardware are also potential sources of security vulnerability. These kinds of vulnerabilities can be unlawfully utilized by attackers and malicious entities for causing damage to the users in different domains. However, discovering such threats is not trivial since simulation-based verification may fail to reveal such corner cases. In this paper, we investigate a formal approach for detecting hardware design errors which can lead to security vulnerabilities. By applying property checking with an industrial strength model checker (JasperGold), we investigate the design of different units of or 1200 processor (5-stage pipeline design) for security threats. By an iterative refinement of properties, we were able to successfully write the security-critical properties of the processor through an understanding of the processor design manuals and specification documents. These properties are written in System Verilog Assertions (SVA) format and provided to the tool for model checking. When the properties fail, we obtain counter-examples that can be analyzed and studied for understanding the issues related to the secure operation of the processor. Model checking experiments were done for a total of thirteen security-critical properties. During our experiments, we also observed some security bugs related to the functionality of or 1200 processor design.