Deep neural network (DNN) weights dominate memory consumption during inference, making their efficient numerical representation particularly important for resource-constrained Edge AI systems. Among commonly used low-bit formats are 8-bit floating-point (FP8) representations such as E5M2 and E4M3. However, these formats span representable ranges that are significantly wider than necessary for typical DNN weights, which exhibit low variance and narrow effective support. Consequently, only a small portion of the format range is utilized. Motivated by the observation that exponent bias scales representable values, we establish a theoretical framework linking FP representation with quantization theory by interpreting FP formats as piecewise-uniform quantizers, enabling systematic investigation of the impact of exponent bias on representation efficiency. This framework enables conversion to low-bit FP representations by establishing encoding and decoding rules and enables analytical estimation of representation accuracy through expressions for the mean squared error and signal-to-quantization-noise ratio (SQNR) as functions of data variance. The analysis shows that SQNR achieves its highest values over a variance range whose width is determined by the exponent–mantissa allocation, while exponent bias controls the position of this high-SQNR region. Based on these insights, we propose an FP8 format for weight representation, termed Bias-Aware FP8 for Weights (BA-FP8-W). This format employs an extended mantissa for higher accuracy and an exponent bias that aligns the high-SQNR region with the variance range of DNN weights. Experimental results on selected DNNs show that the proposed format achieves higher SQNR than E4M3 and E5M2 at the same bit-width and delivers near-FP32 inference accuracy.

Asynchronous Networks-on-Chip (NoCs) offer significant benefits in energy efficiency, area, and modularity, but their lack of compatibility with standard production test flows hinders industrial adoption. This paper demonstrates that a state-of-the-art 2-phase bundled-data asynchronous NoC (TaBuLA) can be transformed and made fully compliant with standard scan-based testing, enabling direct use of unmodified industrial ATPG tools and conventional ATE. Each asynchronous switch component is converted into a synchronous testable abstraction, addressing latch- and FF-related issues and meeting full controllability and observability requirements. As a result, a high-quality stuck-at fault coverage of 96.53% is achieved with a marginal 2% I/O pin count overhead. The unoptimized area, performance and power overheads (2.6x, 1.9x and at most 2x, respectively) achieve a more balanced trade-off between cost-coverage-industrial compliance than previous custom DFT infrastructures for asynchronous NoCs.

FPGA implementation is essential for verifying asynchronous NoCs and validating design requirements. However, prototyping these circuits presents challenges in preserving timing integrity due to mismatches with FPGA timing models. The adoption of bundled-data NoCs with one-sided relative timing constraints further complicates their high-performance mapping. Current CAD flows focus on correctness, but performance optimization is hindered by poor control over timing convergence, leading to overdesigned margins and wasted performance. This paper proposes a methodology that tightly controls relative timing margins through selective net rerouting and delay constraint tuning. On an Artix-7 FPGA using Vivado, the implemented asynchronous NoC switch achieves 40% lower latency and up to 75% lower energy-per-packet than a synchronous counterpart.

Multi-Core neuromorphic processors are becoming increasingly significant due to their energy-efficient local computing and scalable modular architecture, particularly for event-based processing applications. However, minimizing the cost of inter-core communication, which accounts for the majority of energy usage, remains a challenging issue. Beyond optimizing circuit design at lower abstraction levels, an efficient multicast addressing scheme is crucial. We propose a hierarchical bit string encoding scheme that largely expands the addressing capability of state-of-the-art symbol-based schemes for the same number of routing bits. When put at work with a real neuromorphic task, this hierarchical bit string encoding achieves a reduction in area cost by approximately 29% and decreases energy consumption by about 50%.

As digital systems become increasingly integrated into radiation-prone environments, such as aerospace, automotive, and edge computing platforms, their ability to operate reliably under radiation-induced faults is essential. These faults, ranging from transient disruptions to permanent errors, can affect various system layers. In this work, we present an investigation into such challenges, combining simulation-based fault analysis with experimental validation. We introduce a novel methodology for modeling Single Event Transients (SETs) in clock distribution networks, enabling precise evaluation of Flip-Flop (FF) sensitivity. Additionally, a cross-layer framework is introduced to analyze how low-level hardware faults affect inference behavior in Dynamic Neural Networks (DyNNs), highlighting the unique reliability challenges posed by adaptive neural architectures. Finally, we present neutron irradiation results from a soft-core fault-tolerant RISC-V SoC implemented on an SRAM-based FPGA, revealing the critical role of architectural mitigation strategies for Single-Event Upsets (SEUs) and preserving system functionality.

The Special Session on Hardware and Software Solutions for Edge AI Applications at the IEEE MIEL 2025 is being organized as part of the EU-funded Horizon Twinning project “Twinning for Excellence in Adaptive Edge AI” (acronym: AIDA4Edge) [1]–[3]. The project is coordinated by the Faculty of Electronic Engineering, University of Niš (FEEUNI), in partnership with the Leibniz Institute for High Performance Microelectronics (IHP), University of Manchester (UoM), and University of Ferrara (UNIFE). AIDA4Edge started on October 1, 2024, and will run for three years. Its main goal is to strengthen scientific, networking and research management capacity of FEEUNI through an intensive collaboration with the advanced partners, enabling FEEUNI to achieve scientific and innovation excellence in the field of Edge AI. Fig. 1 shows the AIDA4Edge logo, and logos of funding institutions.

On-chip optical wireless links are attracting a great deal of interest as they can provide a possible solution to overcome the drawbacks associated with wired connections. In this paper, we propose a new approach for on-chip communication using optical wireless switches based on thin-film lithium niobate on insulator (LNOI) technology. The optical wireless switches exploit reconfigurable optical phased arrays (OPAs) both at the transmitter and at the receivers. We investigate the radiation characteristics and design criteria of the LN antenna element serving as a unit radiator in the OPAs. We then demonstrate the implementation of an on-chip optical wireless switch in a simple infinite homogeneous host medium and assuming a realistic multilayer structure configuration. Moreover, we examine the impact of various geometrical parameters and the fabrication imperfections on the device performance and provide a discussion on the design optimization. Our findings assess the feasibility of optical wireless switches based on LNOI technology for on-chip wireless communication.

Modern autonomous vehicles have to cope with the consolidation of multiple critical software modules processing huge amounts of real-time data on power- and resource-constrained embedded MPSoCs. In such a highly-congested and dynamic scenario, it is extremely complex to ensure that all components meet their quality-of-service requirements (e.g., sensor frequencies, accuracy, responsiveness, reliability) under all possible working conditions and within tight power budgets. One promising solution consists of taking advantage of complementary resource usage patterns of software components by implementing dynamic resource provisioning. A key enabler of this paradigm consists of augmenting applications with dynamic reconfiguration capability, thus adaptively modulating quality-of-service based on resource availability or proactively demanding resources based just on the complexity of the input at hand. The goal of this paper is to explore the feasibility of such a dynamic model of computation for the critical localization function of self-driving vehicles, so that it can burden on system resources just for what is needed at any point in time or gracefully degrade accuracy in case of resource shortage. We validate our approach in a harsh scenario, by implementing it in the localization module of an autonomous racing vehicle. Experiments show that we can adapt to variations in operational conditions such as the system workload, and that we can also achieve an overall reduction of platform utilization and power consumption for this computation-greedy software module by up to 1.6x and 1.5x, respectively, for roughly the same quality of service.

Biological brains are increasingly taken as a guide toward more efficient forms of computing. The latest frontier considers the use of spiking neural-network-based neuromorphic processors for near-sensor data processing, in order to fit the tight power and resource budgets of edge computing devices. However, a prevailing focus on brain-inspired computing and storage primitives in the design of neuromorphic systems is currently bringing a fundamental bottleneck to the forefront: chip-scale communications. While communication architectures (typically, a network-on-chip) are generally inspired by, or even borrowed from, general purpose computing, neuromorphic communications exhibit unique characteristics: they consist of the event-driven routing of small amounts of information to a large number of destinations within tight area and power budgets. This article aims at an inflection point in network-on-chip design for brain-inspired communications, revolving around the combination of cost-effective and robust asynchronous design, architecture specialization for short messaging and lightweight hardware support for tree-based multicast. When validated with functional spiking neural network traffic, the proposed NoC delivers energy savings ranging from 42% to 71% over a state-of-the-art NoC used in a real multi-core neuromorphic processor for edge computing applications.

Investigating the effects of Single Event Upset in domain-specific accelerators represents one of the key enablers to deploy Deep Neural Networks (DNNs) in mission-critical edge applications. Currently, reliability analyses related to DNNs mainly focus either on the DNNs model, at application level, or on the hardware accelerator, at architecture level. This paper presents a systematic cross-layer reliability analysis of NVIDIA Deep-Learning Accelerator, a popular family of industry-grade, open and free DNN accelerators. The goals are i) to analyze the propagation of faults from the hardware to the application level, and ii) to compare different architectural configurations. Our investigation delivers new insights into the performance-accuracy-reliability trade-off spanned by the configuration space of Deep Learning accelerators. In particular, the Failure in Time can be reduced up to 4.3x for the same DNN model accuracy and by up to 9.4x for the same performance, while accounting 6.5x inference latency and 1.1% accuracy drop, respectively.

Among the emerging technologies, Resistive RAM (RRAM) devices are considered a promising candidate for the replacement of Static RAM (SRAM) cells as memory elements in the interconnection fabric of Field Programmable Gate Arrays (FPGAs). Although previous works have investigated their advantages in terms of performance and energy efficiency, these assessments have focused on fresh devices. In this work, the aging degradation on the propagation delay caused by negative bias-temperature instability (NBTI) effects on different-sized multiplexers (MUXs) is studied under various Process-Voltage-Temperature (PVT) conditions. The comparison between the full-CMOS and the RRAM-based implementations reveals that the traditional SRAM-based design is more affected by aging due to the higher number of transistors.

In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-to-conductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability.

Optical Wireless Networks on-Chip are an emerging technology recently proposed to improve the interconnection between different processing units in densely integrated computing architectures. In this work, we propose a 4 × 4 optical wireless switch (OWS) based on optical phased arrays (OPAs) for broadband reconfigurable on-chip communication. The OPA and OWS design criteria are reported. Moreover, the performances of the OWS are analyzed and optimized considering the electromagnetic propagation in on-chip multilayer structures, with different thicknesses of the cladding layer. The effect on the OWS behavior of a non-ideal distribution of the power in input to the OPA is also investigated by designing a 1 × 7 beam splitter, based on a single-stage multi-mode interference (MMI) device to be used as a single element of the OWS. Then, the MMI output signals are considered in input to the transmitting OPAs and the OWS performances are evaluated.

Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.

Hardware-aware Neural Architectural Search (NAS) is gaining momentum to enable the deployment of deep learning on edge devices with limited computing capabilities. Incorporating device-related objectives such as affordable floating point operations, latency, power, memory usage, etc. into the optimization process makes searching for the most efficient neural architecture more complicated, since both model accuracy and hardware cost should guide the search. The main concern with most state-of-the-art hardware-aware NAS strategies is that they propose for evaluation also trivially infeasible network models for the capabilities of the hardware platform at hand. Moreover, previously generated models are frequently not exploited to intelligently generate new ones, leading to prohibitive computational costs for practical relevance. This paper aims to boost the computational efficiency of hardware-aware NAS by means of a neuro-symbolic framework revolving around a Probabilistic Inductive Logic Programming module to define and exploit a set of symbolic rules. This component learns and refines the probabilities associated with the rules, allowing the framework to adapt and improve over time, thus quickly narrowing down the search space toward the most promising neural architectures.

Optical Wireless Networks on- Chip have been recently proposed as alternative paradigm to overcome the communication bottleneck in computing architectures based on electrical networks. In this paper, we propose the design of a $3\times 3$ switching matrix for optical wireless on- chip interconnection. The design exploits integrated optical phased arrays to guarantee the communication among three transmitters and three receivers. In this work, the effect of multipath propagation in the on- chip multi-layer structure is taken into account, and the impact of the cladding layer thickness is evaluated. The proposed device is intended to interconnect multiple nodes assuring reconfigurability and high bandwidth.

Deep learning accelerator models described with software imperative languages are frequently used for their large-scale reliability analysis in order to overcome the prohibitive simulation times of logic-level and RTL models. However, they are faced with the challenge of preserving consistency between software-visible variables and faulty microarchitectural states. The goal of this work is to determine a suitable accelerator modelling that enables analysis without overloading the simulation engine. Toward this goal, the paper explores different accelerator modelling strategies featuring increasing levels of hardware visibility. They are compared in their capability to gain insights into the reliability of the multiply-and-accumulate (MAC) pipeline of an industry-standard deep learning accelerator from NVIDIA. Our results show that subtle microarchitectural details that are typically overlooked by competing approaches play a relevant role in determining accelerator reliability.

Resistive Random Access Memory (RRAM) devices hold promise to improve the performance of full-CMOS Field Programmable Gate Arrays (FPGAs) exploiting their non-volatility, multilevel nature, small area requirement, and CMOS compatibility for the routing interconnections. Unfortunately, the adoption of this emerging technology is hindered by its intrinsic resistance stochastic behavior. In this work, we investigate how Process-Voltage-Temperature (PVT) variations affect the energy and propagation delay of 4T1R MUX circuits. The comparison with traditional CMOS implementations reveals that for large-sized MUX the RRAM technology is more energy efficient and robust to PVT variations.