The evolution of quantization and mixed-precision techniques has unlocked new possibilities for enhancing the speed and energy efficiency of neural networks (NNs). Several recent studies indicate that adapting precision levels across different parameters can maintain accuracy comparable to full-precision models while significantly reducing computational demands. However, existing embedded microprocessors lack sufficient architectural support for efficiently executing mixed-precision NNs, both in terms of instruction set architecture (ISA) extensions and hardware design. This limitation results in inefficiencies such as excessive data packing/unpacking and underutilized arithmetic units, leading to performance bottlenecks. In this work, to address these challenges, we propose novel ISA extensions and the microarchitecture implementation specifically designed to optimize mixed-precision execution, enabling energy-efficient deep learning inference on RISC-V architectures. We introduce MaRVIn, a cross-layer mixed-precision RISC-V framework for DNN inference that enhances power efficiency and performance through a combination of hardware improvements, mixed-precision quantization, ISA-level optimizations, and cycle-accurate emulation. At the hardware level, we enhance the ALU with configurable mixed-precision arithmetic 2, 4, and 8 bit) for weights and/or activations. To further improve execution efficiency, we employ multipumping to reduce execution latency and implement soft SIMD for efficient 2-bit operations. We also extend ISA to support these mixed-precision operations. At the software level, we integrate a pruning-aware fine-tuning method to optimize model compression. In addition, we introduce a greedy-based design space exploration (DSE) approach to efficiently search for Pareto-optimal mixed-quantized models. Finally, we incorporate voltage scaling to boost the power efficiency of our system. Our extensive experimental evaluation over widely used DNNs and datasets, such as CIFAR10 and ImageNet, demonstrates that our framework can achieve, on average, 17.6 $ imes $ speedup for less than 1% accuracy loss and outperforms the ISA-agnostic state-of-the-art RISC-V cores, delivering up to 1.8 TOPs/W.

The growing demand for affordable, high-capacity memory is driving the adoption of heterogeneous architectures combining DRAM and Non-Volatile Memory (NVM). However, efficiently managing data placement in these systems without introducing significant profiling overhead remains a key challenge. This paper introduces SPID a novel memory management methodology whose core contribution is a low-overhead, spike-based detection mechanism to identify write-intensive execution phases. By focusing on bandwidth spikes where DRAM’s performance advantage is most critical, our approach minimizes continuous profiling costs. This detection enables a multi-objective optimization policy for data placement that simultaneously targets performance, energy efficiency, and NVM lifetime. Evaluated on real hardware across diverse applications, our methodology outperforms industry-standard solutions which act as baseline, and, when comparing against SoA solutions, we achieve 27.8% optimization in performance, 29.13% energy consumption reduction and 30.6% fewer NVM writes on average. Results demonstrate that our spike-based approach is not only effective but also lightweight, flexible and scalable, while requiring optimized profiling and negligible run-time overhead.

Recurrent Neural Networks (RNNs) are vital for sequential data processing. Long Short-Term Memory Autoencoders (LSTM-AEs) are particularly effective for unsupervised anomaly detection in time-series data. However, inherent sequential dependencies limit parallel computation. While previous work has explored FPGA-based acceleration for LSTM networks, efforts have typically focused on optimizing a single LSTM layer at a time. We introduce a novel FPGA-based accelerator using a dataflow architecture that exploits temporal parallelism for concurrent multi-layer processing of different timesteps within sequences. Experimental evaluations on four representative LSTM-AE models with varying widths and depths, implemented on a Zynq UltraScale+ MPSoC FPGA, demonstrate significant advantages over CPU (Intel Xeon Gold 5218R) and GPU (NVIDIA V100) implementations. Our accelerator achieves latency speedups up to 79.6x vs. CPU and 18.2x vs. GPU, alongside energy-per-timestep reductions of up to 1722x vs. CPU and 59.3x vs. GPU. These results, including superior network depth scalability, highlight our approach's potential for high-performance, real-time, power-efficient LSTM-AE-based anomaly detection on FPGAs.

Real-time Doppler Wind LiDAR systems require signal processing architectures capable of balancing accuracy, throughput, and hardware efficiency. In this work, we present a scalable architecture that explores these trade-offs through multiple FPGA implementation configurations. A systematic Design Space Exploration (DSE) was carried out on an AMD Zynq UltraScale+ RFSoC ZCU208 device to examine how processing granularity affects resource utilization and data quality. The implemented designs achieved operating frequencies between 356MHz and 402 MHz. Field experiments against a commercial system confirmed the approach, showing smooth wind speed transitions (across the Line-of-Sight range). Furthermore, the performance of the proposed design is compared against FPGA-based FFT accelerators from other domains, demonstrating strong scalability and efficiency beyond the Wind LiDAR application context.

FPGAs are increasingly being adopted across the edge-to-cloud continuum due to their ability to provide both high performance and energy efficiency. However, the complexity of programming FPGAs often leads to deployed designs that underutilize available resources. FPGA multi-tenancy has been proposed to enhance resource utilization, yet monolithic designs and dynamic workload demands continue to challenge efficient FPGA usage and compliance with Quality of Service requirements. To address these issues, we propose a novel framework for the optimal orchestration of FPGAs across the edge-to-cloud continuum while meeting user demands. The framework generates approximations of Pareto-optimal designs for each application, capturing trade-offs between performance and resource usage with minimal bitstream generation. This information allows the runtime orchestrator to select the most suitable design based on available PR regions and the QoS requirements of each user. Experimental results demonstrate that the proposed approach achieves an average reduction of QoS violations by a factor of 8.1x across diverse workloads and baseline configurations. Overall, the framework offers a practical and effective solution for realizing FPGA-as-a-Service across the edge-to-cloud continuum.

Since the emergence of transformer-based models, the computational demands for Large Language Model (LLM) inference have been increasing exponentially, primarily due to their compounding parameter sizes, their structural complexity, and the use of non-linear functions. This tendency leads to the necessity of deploying them on low-power edge devices and DNN accelerators, to fuel nextgeneration agentic AI systems. Coarse-Grained Reconfigurable Architectures (CGRAs) have proven to be a compelling paradigm for edge acceleration, combining the programmability of general-purpose platforms with the high performance and energy efficiency associated with ASICs. In this work, we introduce an end-to-end performance modeling and mapping framework for LLM inference on heterogeneous CGRAs. Our methodology enables rapid exploration of the micro-architectural design space parameters, i.e., the number of processing elements, vector sizes, and memory configurations, by providing an accurate, explainable, and analytical CGRA performance modeling methodology, with an average cycle error of 0.9%. Architecturally, we build upon R-Blocks, a heterogeneous CGRA platform, and extend it to support floating-point arithmetic operations as well as a full-stack compilation and mapping flow for both full (FP32) and quantized (INT8) Llama2 models. The proposed methodology, evaluated on a 22nm technology node, achieves superior peak performance per Watt compared to related works such as REVAMP and CFEACT (1.8x and 2.8x respectively).

This paper presents a Satellite-As-a-Service (SaaS) architecture designed to enable flexible and efficient deployment of Machine Learning (ML) workloads on heterogeneous edge hardware platforms in space. Leveraging container-based virtualization (Docker) and an orchestration framework (Kubernetes), our approach abstracts hardware complexity and supports a variety of accelerators — FPGAs, TPUs, VPUs and NPUs —within a unified development and deployment environment. We integrate DevOps design principles delivering a reconfigurable stack that supports rapid ML model updates and deployment on target hardware. By treating satellites as extensible service platforms, we demonstrate how containerization and hardware abstraction streamline the onboarding of advanced ML algorithms, ranging from convolutional neural networks for image processing to neuromorphic paradigms for ultra-low-power inference. We detail how standardized APIs and modular workflows promote interoperability across multiple satellite systems and heterogeneous hardware accelerators. Overall, the presented SaaS architecture offers a pathway toward smarter, more versatile satellite payload operations, shaping the next generation of inorbit data processing and autonomy.

Recent advances in applications that are highly dependent on efficient cache utilization, in addition to the rapid growth of Edge computing systems deployed with emerging processors, generate a complex paradigm across the hardware and software continuum. In this work, we propose ARC, a novel systematic exploration methodology for application-level refinement and cache configuration mapping over emerging architectures for performance optimization. More specifically, our solution relies on workload partitioning and source code slicing mechanisms aiming to boost co-exploration of cache configuration parameters. Our proposed methodology is evaluated on a real-life IoT biomedical use case deployed over GEM5 RISC-V simulated system, showing that i) the co-impact of source code refinement and effective cache configuration leads to 61.1% execution time optimization, ii) the effective application organization and refinement leads to reduced hardware complexity. Last, we provide guidelines for application cache-friendly source code organization for performance optimization.

The need for increased memory capacity, which is also affordable and sustainable, leads to the adoption of heterogeneous memory hierarchies, combining DRAM and NVM technologies. This work proposes a memory management methodology that relies on multi-objective optimization in terms of performance, energy consumption and impact on NVM’s lifetime, for applications deployed on heterogeneous (i.e. DRAM/NVM) memory systems. The evaluation of the methodology was performed both on emulated and real DRAM/NVM hardware for different applications and data placement algorithms. The experimental results show 58.7% lower execution time, 48.3% less energy consumption and 72.6% less NVM write operations compared to the results obtained by the initial versions of the applications. Thorough evaluation shows that the methodology is flexible and scalable, as it can integrate different data placement algorithms and NVM technologies and requires reasonable exploration time.

Printed Electronics (PE) provide a flexible, cost-efficient alternative to silicon for implementing machine learning (ML) circuits, but their large feature sizes limit classifier complexity. Leveraging PE's low fabrication and NRE costs, designers can tailor hardware to specific ML models, simplifying circuit design. This work explores alternative arithmetic and proposes a hybrid unary-binary architecture that removes costly encoders and enables efficient, multiplier-less execution of MLP classifiers. We also introduce architecture-aware training to further improve area and power efficiency. Evaluation on six datasets shows average reductions of 46

Computational-neuroscience simulators have traditionally been constrained by tightly coupled simulation engines and modeling languages, limiting their flexibility and scalability. Retrofitting these platforms to accommodate new backends is often costly, and sharing models across simulators remains cumbersome. This paper puts forward an alternative approach based on the EDEN neural simulator, which introduces a modular stack that decouples abstract model descriptions from execution. This architecture enhances flexibility and extensibility by enabling seamless integration of multiple backends, including hardware accelerators, without extensive reprogramming. Through the use of NeuroML, simulation developers can focus on high-performance execution, while model users benefit from improved portability without the need to implement custom simulation engines. Additionally, the proposed method for incorporating arbitrary simulation platforms—from model-optimized code kernels to custom hardware devices—as backends offers a more sustainable and adaptable framework for the computational-neuroscience community. The effectiveness of EDEN's approach is demonstrated by integrating two distinct backends: flexHH, an FPGA-based accelerator for extended Hodgkin-Huxley networks, and SpiNNaker, the well-known, neuromorphic platform for large-scale spiking neural networks. Experimental results show that EDEN integrates the different backends with minimal effort while maintaining competitive performance, reaffirming it as a robust, extensible platform that advances the design paradigm for neural simulators by achieving high generality, performance, and usability.

In any telecommunication system, it is crucial to have a high-performance receiver to meet the desired requirements. However with the newer protocols demanding high order constellations, the demodulation process in the receiver becomes a bottleneck. To facilitate the implementation of telecommunication systems on embedded platforms, in this work we explore optimizations to the QAM demodulation, by applying SIMD operations with the NEON engine along with algorithmic approximation techniques. We implement a NEON-based Demodulator using the Approximate LLR algorithm, while we also propose an approximate method for QAM16/QAM64 that focuses on one quadrature for calculating the required Euclidean distances, along with the respective NEON accelerator. We perform a trade-off analysis between system’s BER and execution time of the Demodulator and the receiver module for the base and approximate implementations, while also exploring the impact of different bit widths and precision in computations. We demonstrate that our approximate technique can achieve × 18 – × 37 speedup over the original algorithm without BER deviations on uncoded channels, while the use of LDPC is also examined.

We present a novel scheduling framework for energy-efficient video analytics at the edge. The proposed approach dynamically adjusts GPU frequency and batch size to optimize inference execution while ensuring QoS compliance. It integrates a priority queue for QoS-aware scheduling and leverages offline profiling and ML-based estimation to select energy-optimal configurations. Based on these configurations, it employs a priority-based scheduler with greedy batching and adaptive waiting strategies to efficiently dispatch inference requests. Experimental evaluation conducted on an NVIDIA Jetson Xavier AGX device demonstrates a similar to 28% improvement in frames served per joule compared to a baseline with no scheduler. This outperforms a static batch scheduler (32 frames per batch) by similar to 15% and a time-triggered scheduler (batch formation every 200 ms) by similar to 29%, while introducing minimal increase in QoS violations (5%) relative to the best-performing policy.

The ever-increasing complexity and operational diversity of modern Neural Networks (NNs) have caused the need for low-power and, at the same time, high-performance edge devices for AI applications. Coarse Grained Reconfigurable Architectures (CGRAs) form a promising design paradigm to address these challenges, delivering a close-to-ASIC performance while allowing for hardware programmability. In this paper, we introduce a novel end-to-end exploration and synthesis framework for approximate CGRA processors that enables transparent and optimized integration and mapping of state-of-the-art approximate multiplication components into CGRAs. Our methodology introduces a per-channel exploration strategy that maps specific output features onto approximate components based on accuracy degradation constraints. This enables the optimization of the system's energy consumption while retaining the accuracy above a certain threshold. At the circuit level, the integration of approximate components enables the creation of voltage islands that operate at reduced voltage levels, which is attributed to their inherently shorter critical paths. This key enabler allows us to effectively reduce the overall power consumption by an average of 30 compared to their baseline counterparts, while incurring only a minimal 2 overhead. The proposed methodology was evaluated on a widely used NN model, MobileNetV2, on the ImageNet dataset, demonstrating that the generated architectures can deliver up to 440 GOPS/W with relatively small output error during inference, outperforming several State-of-the-Art CGRA architectures in terms of throughput and energy efficiency.

The evolution of mobile networks (5G/B5G) relies on different hybrid transport architectures that enable flexible and scalable interconnection between devices and services with different interfaces and requirements. Despite significant improvements in data rates, device capabilities and data volumes compared to previous generations, technology choices are still under consideration and new proposals are constantly emerging. To address these challenges, Int5Gent proposes and develops a 5G/B5G system that integrates innovative data plane technology building blocks within a flexible orchestration framework. The proposed platform provides a complete 5G system for validating advanced services and Internet of Things solutions, facilitating the transition beyond current 5G network capabilities, and evaluating state-of-the-art data transport and edge processing solutions.

Federated Learning (FL) enables collaborative model training across distributed, privacy-sensitive data sources. Traditional FL follows a centralized client-server architecture, relying on synchronized updates and uniform participation. However, real-world deployments face challenges such as client heterogeneity, stragglers, non-independent data distributions, and single points of failure due to server centralization. To address these limitations, we propose an asynchronous Peer-to-Peer FL scheme that enhances learning efficiency in heterogeneous environments. Our method employs a gradient-aware aggregation algorithm with a progress-based adaptive fusion weight, mitigating the impact of resource disparities among clients. Experimental results on CIFAR-10/100 datasets indicate that our scheme achieves 4.8 - 16.3% and 10.9 - 37.7% higher accuracy compared to FedAVG and FedSGD, considering constrained total number of exchanged updates among clients. Furthermore, it effectively handles client heterogeneity through its dynamic fusion weight adjustment.

The current work presents an Edge Computing hardware accelerator for real-time signal processing in Coherent Doppler Wind Lidars (CDWLs). CDWLs require high-sampling rates that exceed 7 Gbit/s in data throughput for distances above 7.5 km, considering the raw and the accumulated data for noise suppression. The proposed solution exploits a reconfigurable hardware accelerator (Xilinx UltraScale+ MPSoC ZCU102 FPGA) that instantiates 16 parallel processing chains estimating in real-time the wind Doppler shift. The deployed system traces wind speed in 2-digit precision up to 9.99 km range with a spatial resolution of 39.03 m. The hardware accelerator is operating at 245.76 MHz, attaining a processing throughput of 41.94 Gbit/s and utilizing 80210 LUTs, 553 BRAMs and 640 DSPs.

Indoor positioning is an ever-evolving IoT research topic that is expected to usher in a new era for the way we interact with environments such as theatres, shopping malls, airports, hospitals, etc. Bluetooth-based solutions present numerous advantages, given the widespread use of Bluetooth-enabled devices like smartphones and wearables by a majority of individuals on a daily basis. The positioning is achieved through Bluetooth beacons, small devices that consistently emit Bluetooth signals, detectable by smartphones or other compatible devices. In this article, the use of Bluetooth technology for indoor positioning is examined and a hybrid method based on both AoA (angle of Arival) and RSSI signals is introduced. Finally, a navigation mobile application for enhancing the accessibility of a theater environment to the visually impaired people is demonstrated.

The emerging need for fast and power-efficient AI/ML deployment on-board spacecraft has forced the space in-dustry to examine specialized accelerators, which have been suc-cessfully used in terrestrial applications. Towards this direction, the current work introduces a very heterogeneous co-processing architecture that is built around UltraScale+ MPSoC and its programmable DPU, as well as commercial AI/ML accelerators such as MyriadX VPU and Edge TPU. The proposed architecture, called MPAI, handles networks of different size/complexity and accommodates speed-accuracy-energy trade-offs by exploiting the diversity of accelerators in precision and computational power. This brief provides technical background and reports preliminary experimental results and outcomes.