Compiler-parallelized applications are increasing in importance as moderate-scale multiprocessors become common. This paper evaluates how features of advanced memory systems (e.g., longer cache lines) impact memory system behavior for applications amenable to compiler parallelization. Using full-sized input data sets and applications taken from the SPEC, NAS, PERFECT, and RICEPS benchmark suites, we measure statistics such as speedups, memory costs, causes of cache misses, cache line utilization, and data traffic. This exploration allows us to draw several conclusions. First, we find that larger granularity parallelism often correlates with good memory system behavior, good overall performance, and high speedup in these applications. Second, we show that when long (512 byte) cache lines are used, many of these applications suffer from false sharing and low cache line utilization. Third, we identify some of the common artifacts in compiler-parallelized codes that can lead to false sharing or other types of poor memory system performance, and we suggest methods for improving them. Overall, this study offers both an important snapshot of the behavior of applications compiled by state-of-the-art compilers, as well as an increased understanding of the interplay between cache line size, program granularity, and memory performance in moderate-scale multiprocessors.

We have recently released the SPLASH-2 suite of parallel applications for the study of centralized and/or distributed shared-address-space multiprocessors. In this regard, this paper has two main goals. One is to quantitatively characterize the SPLASH-2 programs in terms of fundamental properties that are important to understanding these parallel programs, and to describe how these properties vary with problem and machine parameters. The properties we study include the concurrency and load balance behavior, the communication-to-computation ratio, the sizes and scaling of the important working sets, and issues related to spatial locality. The other, perhaps more important, goal is methodological: to assist people who will use the programs for architectural evaluations to prune the design space of machine parameters in an informed and meaningful way. For example, by characterizing the working sets of the applications, we describe which operating regions in terms of cache size and problem size are representative of realistic situations and which are not (as well as which are redundant). Using SPLASH-2 as an example, we also hope to convey the importance of understanding the interplay of problem size, number of processors, and working sets in designing experiments and interpreting their results.

We have recently released the SPLASH-2 suite of parallel applications for the study of centralized and/or distributed shared-address-space multiprocessors. In this regard, this paper has two main goals. One is to quantitatively characterize the SPLASH-2 programs in terms of fundamental properties that are important to understanding these parallel programs, and to describe how these properties vary with problem and machine parameters. The properties we study include the concurrency and load balance behavior, the communication-to-computation ratio, the sizes and scaling of the important working sets, and issues related to spatial locality. The other, perhaps more important, goal is methodological: to assist people who will use the programs for architectural evaluations to prune the design space of machine parameters in an informed and meaningful way. For example, by characterizing the working sets of the applications, we describe which operating regions in terms of cache size and problem size are representative of realistic situations and which are not (as well as which are redundant). Using SPLASH-2 as an example, we also hope to convey the importance of understanding the interplay of problem size, number of processors, and working sets in designing experiments and interpreting their results.

Compiler-parallelized applications are increasing in importance as moderate-scale multiprocessors become common. This paper evaluates how features of advanced memory systems (e.g., longer cache lines) impact memory system behavior for applications amenable to compiler parallelization. Using full-sized input data sets and applications taken from the SPEC, NAS, PERFECT, and RICEPS benchmark suites, we measure statistics such as speedups, memory costs, causes of cache misses, cache line utilization, and data traffic. This exploration allows us to draw several conclusions. First, we find that larger granularity parallelism often correlates with good memory system behavior, good overall performance, and high speedup in these applications. Second, we show that when long (512 byte) cache lines are used, many of these applications suffer from false sharing and low cache line utilization. Third, we identify some of the common artifacts in compiler-parallelized codes that can lead to false sharing or other types of poor memory system performance, and we suggestmethods for improving them. Overall, this study offers both an important snapshot of the behavior of applications compiled by state-of-the-art compilers, as well as an increased understanding of the interplay between cache line size, program granularity, and memory performance in moderate-scale multiprocessors.

The SPLASH-2 suite of parallel applications has recently been released to facilitate the study of centralized and distributed shared-address-space multiprocessors. In this context, this paper has two goals. One is to quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well. The properties we study include the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality, as well as how these properties scale with problem size and the number of processors. The other, related goal is methodological: to assist people who will use the programs in architectural evaluations to prune the space of application and machine parameters in an informed and meaningful way. For example, by characterizing the working sets of the applications, we describe which operating points in terms of cache size and problem size are representative of realistic situations, which are not, and which re redundant. Using SPLASH-2 as an example, we hope to convey the importance of understanding the interplay of problem size, number of processors, and working sets in designing experiments and interpreting their results.