Stochastic Computing (SC) is a computational technique that executes arithmetic operations on a random bitstream basis. Traditionally, stochastic arithmetic circuits are found according to probability equations, however not all arithmetic operations can directly be generated using this technique. This paper introduces a sequential processing technique to design SC arithmetic circuits in unipolar encoding format. The proposed technique processes each bit of data in the input bitstream by considering the previous information. The output bitstream can then easily be generated. A SC adder, a SC subtractor, a SC comparator, a SC absolute subtractor, a SC multiplier by integer, and a SC divider by integer are proposed. The proposed technique provides many advantages over the traditional methods such as ease of design, flexibility, reductions in limitations when generating arithmetic functions, and efficient circuits. Moreover, the value of the output signal can be read without the need to multiply the result. The impact of each parameter in the proposed SC arithmetic circuits is studied to assess the accuracy of the proposed SC circuit; then, a comparison between the proposed and other SC circuits is presented. The results in this paper show that the proposed designs are significantly better than other SC arithmetic circuits in terms of accuracy, correlation between input signals to the output data, and cross-correlation to input signals, area, delay, power dissipation, and power delay product (PDP). For example, in the proposed SC adder circuit, its accuracy is improved by 64.67% while its delay, power dissipation, area, and PDP are improved by 45.79%, 85.86%, 85.60%, and 92.33% respectively.

The Traveling Salesman Problem (TSP) continues to attract significant research interest due to its critical role in various applications. This paper introduces a recursive clustering approach that divides cities into a limited number of clusters, each containing up to five cities and its own centroid. Constrained TSP and simulated annealing techniques are employed to route cities within each cluster, using the centroids of neighboring clusters as entry and exit points for the routing process. This method offers the benefit of producing accurate and cost-effective routing solutions, due to the reduced number of cities in each cluster. The connections between cluster centroids are established using simulated annealing. The FPGA-based proposed hardware implementation demonstrates the feasibility of routing a large number of cities, as the approach leverages memory to store cluster information. Consequently, the method is independent of the FPGA's logic hardware, and its scalability depends on the FPGA's memory capacity. Furthermore, distance calculations using approximate methods for the FPGA execution are compared and the squared Euclidean is chosen due to its low resources' utilization. Compared to previous methods, the proposed approach can handle more cities for routing, offering better scalability and a higher operating frequency.

As widely used in arithmetic circuits (such as a ripple carry adder [RCA]), approximate computing intentionally introduces errors in the design; however, approximate circuits can also experience errors due to external and physical phenomena (such as cosmic rays or a stuck-at). These errors can be analyzed by their functional nature. This article examines the impact of a single functional error (SFE) in both an approximate cell as well as the entire RCA. The study analyzes exact and approximate cell designs using a state transition diagram-based approach to understand the relationships between different types of functional error and the expected behavior in all possible scenarios. The article also proposes a probabilistic analysis for an exact RCA, which aligns well with simulation results for several metrics, such as the error rate (ER). Additionally, an error analysis is conducted on the RCA by considering the number of approximate cells and the location of the single erroneous cell. The results and modeling analysis of the exact RCA show that the ER and the mean error distance (MED) for Carry in (Cin) = 0 are higher than for Cin = 1; furthermore, the MED for an approximate RCA in the presence of an SFE is higher than for the exact RCA. These findings indicate that an approximate RCA affected by an SFE incurs a significantly degraded accuracy as related to the approximate cell type. Finally, the article provides a binary tree-based analysis to support the comprehensive simulation results for the RCA’s ER using different approximate cells.

Data compression with Huffman codes has been commonly employed to reduce the memory size required for emerging applications with large storage needs, such as Machine Learning (ML). However, memories at the nanoscale can suffer from errors, causing data corruption. This issue is even more severe for memories storing compressed data, because the error can propagate after decompression. This paper proposes an efficient error-resilient data compression scheme applicable to nanoscale memories by employing interleaved data storage and Huffman coding. Based on the evaluation results on protecting two compressed ML models, this scheme reduces the memory overhead by over 99% compared to conventional error protection schemes (such as parity or Hamming codes), while limiting the accuracy loss in the range of 0.26% to 3.27%.

Energy of Convolutional Neural Network (CNN) accelerators is mostly dissipated by arithmetic operations and memory accesses, SRAM dynamic power being the largest component. Multiplication-free operators (OPs) like the Sum-of-Absolute-Difference (SAD) reduce computational energy, while a lower memory voltage reduces memory energy—yet voltage reduction increases the bit error rate (BER), so requiring OPs to have inherent error tolerance. To address these concerns, this paper proposes a hardware-oriented Neural Architecture Search (NAS) framework for OP-level multi-objective optimization of accuracy, computational energy, and memory energy. Its search space consists of efficient multiplication-free primitives; via regularized evolution with NSGA-III selection, the framework automatically synthesizes novel OPs. An extensive evaluation on various CNNs (ResNet-20/32/50Lite, EEGNet, SimpleViT) and datasets (CIFAR-10/100, ImageNet variants, EEG signals) shows that the discovered OPs match the accuracy of standard Multiply-Accumulate (MAC) and SAD baselines. Notably, OP-6 consumes only 0.0108 pJ/op under an 8-bit quantization at 28nm technology node. For the ResNet-20/CIFAR-10 task, OP-6 reduces the total system energy (compute and memory) by 58% versus the baseline. This work establishes an automated co-design paradigm for ultra-low-power, highly dependable CNN accelerators for edge deployment.

Recent developments in artificial neural networks (ANNs) have resulted in applications requiring the integration of power and computational efficiency without compromising model accuracy. As a compromise between hardware metrics and numerical accuracy, the mixed-precision floating-point (FP) calculation has been developed. In this work, the design of several computational operations during inference and training of ANNs has been proposed; this includes an FMA-based multiply-accumulation unit design that supports neuron computation with mixed-precision, and an efficient normalization unit based on novel schemes of FP division and square root designs. Evaluation results verify the benefits of the proposed design in terms of computational accuracy and operational latency. Also, several metrics are compared for different popular FP precision formats to show that the final accuracy can be leveraged by choosing the proper precision.

Data compression with Huffman codes has been commonly employed to reduce the memory size required for emerging applications with large storage needs, such as Machine Learning (ML). However, memories at the nanoscale can suffer from errors, causing data corruption. This issue is even more severe for memories storing compressed data, because the error can propagate after decompression. This paper proposes an efficient error-resilient data compression scheme applicable to nanoscale memories by employing interleaved data storage and Huffman coding. Based on the evaluation results on protecting two compressed ML models, this scheme reduces the memory overhead by over 99% compared to conventional error protection schemes (such as parity or Hamming codes), while limiting the accuracy loss in the range of 0.26% to 3.27%.

Large language models are capable of solving complex math problems or answering difficult questions on almost any topic, but can they generate random street addresses for European cities?

Language Models (LLMs) pose significant challenges in terms of speed and energy dissipation of AI systems. Dependability is a further important issue for LLM implementations; this is especially relevant for FPGAs that are vulnerable to soft errors in the configuration memory. Moreover, as current GPU based implementations are not energy efficient, there is interest in running LLMs on different technology platforms, such as FlightLLM (an FPGA based accelerator designed to run LLMs for energy efficiency). In this paper, we analyze and evaluate the robustness of FPGA-based LLMs against faults/errors in the config-uration memories. For the evaluation, we first propose a PyTorch based fault injection simulator and based on the analysis of FlightLLM and we study its robustness against stuck-at faults on the configuration memory. Furthermore, we propose an efficient error detection technique based on a concurrent classifier. Evaluation results show that stuck-at errors on high bits of the logic units can dramatically degrade the LLM performance, and the proposed concurrent classifier can effectively detect errors with negligible complexity and overhead. Finally, a low-cost fault location scheme is proposed, so that the fault can be easily recovered by dynamic partial reconfiguration. The combination of the concurrent classifier error detection and fault location can be used to improve the robustness of a FPGA-based LLM efficiently, such as FlightLLM.

Transformers are widely used in natural language processing and computer vision, and Bidirectional Encoder Representations from Transformers (BERT) is one of the most popular pre-trained transformer models for many applications. This paper studies the dependability and impact of soft errors on BERT implemented with different floating-point formats using two case studies: sentence emotion classification and question answering. Simulation by error injection is conducted to assess the impact of errors on different parts of the BERT model and different bits of the parameters. The analysis of the results leads to the following findings: 1) in both single and half precision, there is a Critical Bit (CB) on which errors significantly affect the performance of the model; 2) in single precision, errors on the CB may cause overflow in many cases, which leads to a fixed result regardless of the input; 3) in half precision, the errors do not cause overflow but they may still introduce a large accuracy loss. In general, the impact of errors is significantly larger in single-precision than half-precision parameters. Error propagation analysis is also considered to further study the effects of errors on different types of parameters and reveal the mitigation effects of the activation function and the intrinsic redundancy of BERT.

Stochastic computing (SC) has emerged as an efficient low-power alternative for deploying neural networks (NNs) in resource-limited scenarios, such as the Internet of Things (IoT). By encoding values as serial bitstreams, SC significantly reduces energy dissipation compared to conventional floating-point (FP) designs; however, further improvement of layer-wise mixed-precision implementation for SC remains unexplored. This article introduces Adjustable Sequence Length (ASL), a novel scheme that applies mixed-precision concepts specifically to SC NNs. By introducing an operator-norm-based theoretical model, this article shows that truncation noise can cumulatively propagate through the layers by the estimated amplification factors. An extended sensitivity analysis is presented, using random forest (RF) regression to evaluate multilayer truncation effects and validate the alignment of theoretical predictions with practical network behaviors. To accommodate different application scenarios, this article proposes two truncation strategies (coarse-grained and fine-grained), which apply diverse sequence length configurations at each layer. Evaluations on a pipelined SC MLP synthesized at 32nm demonstrate that ASL can reduce energy and latency overheads by up to over 60% with negligible accuracy loss. It confirms the feasibility of the ASL scheme for IoT applications and highlights the distinct advantages of mixed-precision truncation in SC designs.

This paper proposes new designs of double modular redundancy (DMR) when time-continuous data is provided as inputs. As this type of data tends slightly change over adjacent time periods, the proposed designs exploit this property by comparing consecutive outputs for reliable computing. The proposed designs are based on the difference between the two consecutive inputs/outputs, referred to as factor. These new designs are four one-factor and a single two-factor scheme. They overcome the negative feature of a previous design (referred to as self-voting) by which an uncontrollable output is encountered when input data is time-continuous and both primary inputs are not equal, i.e. in the presence of an error, the output remains at the same value prior to the occurrence of the error, so making it unsuitable for these types of applications. The proposed designs are evaluated in terms of the required decision hardware (to generate the output) and its accuracy using Cadence Genus Synthesis Solution on a 32 nm library; it is shown that the decision hardware of the two-factor scheme is more complex than for the one-factor schemes, yielding to a longer delay and higher power dissipation/area. Different data sets as well as a randomly generated data set are utilized in the evaluation. Simulation results show that the two-factor scheme provides the highest level of accuracy at the output as this is directly related to the complexity of the decision hardware:

As an approximate membership query filter, the XOR Filter (XF) offers advantages such as smaller memory requirements and faster operation in some settings compared to other filters such as Bloom Filters and Cuckoo Filters. However, a concern still remains on the dependability of XFs in critical applications; soft errors, such as a Single Event Transient (SET) and a Single Event Upset (SEU), can cause errors in the hardware or stored data, leading to false positives or false negatives in the XF queries. This paper first performs a theoretical analysis of XF's dependability under SETs and SEUs, and then performs simulations to verify the results of the analysis. The evaluation shows that soft errors have almost no effect on false positives, but they can cause harmful false negatives in XFs.