In this article, we propose a lightweight axial-depthwise network (LADNet) to address interference fading and large-dynamic-range phase wrapping in phase-sensitive optical time-domain reflectometry (phi-OTDR). The lightweight design leverages axis-specific patterns and local spatial correlation in phi-OTDR waterfall data and captures these features using axial depthwise (DW) convolutions. We design a U-Net architecture that integrates multibranch axial DW convolutions and attention mechanisms to capture the anisotropic spatiotemporal correlations of phi-OTDR signals. To construct paired data for training and evaluation, we generate noisy wrapped-phase samples with fading and corresponding unwrapped-phase references using a physics-driven phi-OTDR simulator. On simulated test data (strain range: 0-500 n epsilon), LADNet achieves a strain MAE of 1.3 ne with only 1.70M parameters. Experiments on a 5.6-km phi-OTDR system further verify robust phase recovery under large-amplitude vibration, yielding an SNR of 32.2 dB and a strong linear relationship between the recovered phase and the PZT driving voltage (R-2 = 0.9974). Overall, the proposed method provides an effective solution for phase demodulation in phi-OTDR under large amplitude vibration conditions.

A least-squares power profile estimation method via DSP frame pilot symbols is proposed, requiring no post-FEC symbols while remaining offset-free. Experiments on 80 GBaud DP-16QAM links closely match ideal-reference results, promising for practical deployment.

Merkle Tree is a fundamental cryptographic primitive in Zero-Knowledge Proof (ZKP) protocols, sharing significant computational workloads with the Number Theoretic Transform (NTT) in zk-STARK schemes. Merkle Tree is a tree structure where nodes are primarily generated through hash computations. Among them, Poseidon Hash, as a ZK-friendly hash function, has emerged as one of the most widely adopted choices. Therefore, hardware acceleration of building Merkle Tree based on Poseidon Hash can significantly enhance the performance of ZKP protocols. We propose AcclMT, a highly resource-efficient and flexible Poseidon Hash-based Merkle Tree architecture. Our design employs hardware-software co-design and optimizes the hashing data flow, resulting in an area-efficient Poseidon Hash engine that improves modular multiplication resource utilization. Furthermore, AcclMT uses these engines alongside hierarchical on-chip cache and optimized task scheduling for building large Merkle Trees. It also supports flexible parameter configurations for various requirements. Experimental results show that our proposed Poseidon Hash engine achieves a 14.3 x speedup compared to the latest FPGA-based work. By improving resource utilization, it also reduces area usage by 14.8% compared to unoptimized design. AcclMT achieves up to 1665 x speedup over software implementations in building Merkle tree, with average utilization of 95.9% and 99.2% for the two hash engines.

In modern machine learning models like Transformers, matrix multiplication dominates most computation. Specific hardware often uses large-scale PE arrays, such as systolic arrays, to accelerate this process. However, these extensive PE arrays tend to experience high fault rates, with cumulative errors in matrix multiplication potentially impacting final algorithmic outcomes. We propose GEMMHeal, a self-repairing, systolic-array-like architecture optimized for matrix multiplication. This architecture optimizes the matrix multiplication array design and data flow in the buffer while decoupling the error correction (EC) core from the array. The EC core operates as an independent computation unit, maintaining resource efficiency and avoiding performance degradation due to the spatial locality of faults. Additionally, our proposed design incorporates redundancy within the EC core, allowing it to self-repair and thus further improve fault tolerance. GEMMHeal is implemented in a 32nm process to demonstrate its area and physical achievability. A single EC core occupies only 1.8% of the area while effectively repairing up to 6.3% of faulty PEs, all while maintaining overall performance. By accounting for potential faults within the EC core, our redundant design achieves an average improvement of 31% in the EC core normal rate compared to non-redundant designs when the computation cell fault rate is within 15%.

The routing architecture significantly impacts the performance of modern FPGAs, motivating extensive research into its design space exploration (DSE). However, DSE efficiency is hindered by non-generalizable parametrization methods and considerable runtime overhead of FPGA architecture evaluation tools. In this paper, we propose GEF, a GNN-based FPGA Evaluation Framework that predicts routability and area-delay product (ADP) across various routing architectures. In GEF, we introduce Intra-Tile Graph, a novel intermediate representation (IR) that encodes global routing patterns in a compact form, serving as the input to predictors. The Routability Predictor (Rou-P) integrates Self-Attention Pooling (SAGPool), while the ADP Predictor (ADP-P) benefits from intermediate supervision through auxiliary node-level labels. Experimental results demonstrate the high accuracy of GEF, with Rou-P achieving 94.56% and ADP-P 94.57%, respectively. We also conduct ablation studies, which further validate that GEF achieves substantial enhancements through efficient architecture modeling and timingaware analysis. Finally, a case study on routing architecture exploration with the incorporation of GEF is presented, which achieves a 15x speedup and enhanced improvements.

Zero-knowledge proof (ZKP) is a widely used privacy-preserving technology, where multiscalar multiplication (MSM) accounts for over 70% of the computational workload. The acceleration of MSM can enhance the overall performance of ZKP, making it a focal point of community attention. However, in practical applications involving the deployment of multiple MSM accelerators, existing designs often overlook strategies for optimizing bandwidth and area efficiency. To address this, we propose Myosotis, an efficiently pipelined and parameterized MSM architecture. By sharing input data and allocating cache effectively, it mitigates average transmission bandwidth in runtime. Myosotis also supports the use of multiple point addition (PADD) units to achieve performance gains, balancing area overhead and latency for improved area efficiency. Different parameter selection enables a tradeoff between the performance, area, and bandwidth of the MSM accelerator. When benchmarking with MSM degrees between 2(18) and 2(26) , our proposed baseline design achieves up to 3.32x and 6.72x speedups over state-of-the-art FPGA and ASIC designs. Compared to the baseline, Myosotis with two window MSMs and one PADD unit reduces bandwidth demand by 43% while maintaining similar area and latency. On the other hand, Myosotis with three window MSMs and two PADD units decreases latency by 43% and bandwidth by 17%, with only a 9% area increase.

Graph Convolutional Networks (GCNs) have demonstrated significant potential in fields such as link prediction and personalized recommendation. However, when applied to deep architectures, GCNs often suffer from accuracy decline and increased computational complexity, while lacking hardware-level optimizations tailored for deep GCNs. This paper introduces D-GCN, a dynamic pruning accelerator for deep GCNs with hybrid dataflow. The dynamic pruning mechanism enables early node convergence through distance computations, significantly reducing computational complexity and mitigating accuracy decline. Leveraging a hybrid dataflow to restructure the feature update process, D-GCN integrates distance computations directly into the feature update pipeline, enabling efficient dynamic pruning in hardware while reducing off-chip memory access. D-GCN effectively captures the benefits of deeplayer node convergence through dynamic pruning and achieves hardware-level optimizations tailored for deep GCNs. Experimental results show that D-GCN can achieve 1.5x speedup and 1.3x energy efficiency compared to the SOTA GCN accelerator. Compared to GPUs, D-GCN achieves an average of 19.2x speedup and 105.8x energy efficiency on deep GCNs, respectively.

In privacy-preserving applications like Post-Quantum Cryptography (PQC) and Fully Homomorphic Encryption (FHE), polynomial multiplication is common, and the Number Theoretic Transform (NTT) is a key algorithm for reducing its complexity. In this paper, we present HMNTT, a highly efficient MDC-NTT architecture. Utilizing the four-step NTT algorithm and a pipelined transpose module, HMNTT offers a highly efficient and scalable architecture for handling NTT with large degrees. We optimize the processing element (PE) to alleviate backpressure and data conflicts in data flow. Leveraging FPGA characteristics, we construct a modular multiplication module to reduce resource usage and improve operating frequency. Evaluation results indicate that HMNTT achieves an average of 2.34x and 1.26x reduction in Area-Time Product compared to the latest pipelined NTT architectures.

Multi-Scalar Multiplication (MSM) is a fundamental cryptographic primitive, which plays a crucial role in Zero-knowledge proof systems. In this paper, we optimize the single MSM Process Element (PE) utilizing buckets with fewer conflicts, enhanced by Greedybased scheduling, to achieve higher efficiency. The evaluation results show our optimized single MSM PE achieving a speedup of over two times on average, peaking at 3.63 times compared to previous works. Furthermore, we introduce Gypsophila, a scalable and bandwidth-optimized architecture for implementing multiple MSM PEs. Leveraging the characteristics of the bucket method, we optimize the data flow by balancing the throughput of bucket classification, bucket aggregation, and result aggregation in MSM. Simultaneously, multiple PEs with different data access patterns share a universal point input channel and post-processing unit, which improves the module utilization and mitigates the bandwidth pressure. Gypsophila with 16 PEs, accomplishes 16 MSM tasks in a mere 1.01% additional time, showcasing an approximate 7.8% reduction in area, with only about 1 16 of the bandwidth requirement, compared with 16 PEs without input channel and post-process unit sharing.

Field-programmable gate arrays (FPGAs) are an ideal candidate for accelerating graph neural networks (GNNs). However, the FPGA redeployment process is time-consuming when updating or switching between diverse GNN models across different applications. Existing GNN processors eliminate the need for FPGA redeployment when switching between different GNN models. However, adapting matrix multiplication types by switching processing units decreases hardware utilization. In addition, the bandwidth of DDR limits further improvements in hardware performance. This article proposes a highly flexible FPGA-based overlay processor for GNN accelerations. Graph-OPU provides excellent flexibility and programmability for users, as the executable code of GNN models is automatically compiled and reloaded without requiring FPGA redeployment. First, we customize the compiler and instruction sets for the inference process of different GNN models. Second, we customize the datapath and optimize the data format in the microarchitecture to fully leverage the advantages of high bandwidth memory (HBM). Third, we design a unified matrix multiplication to handle both sparse-dense matrix multiplication (SpMM) and general matrix multiplication (GEMM), enhancing Graph-OPU performance. During Graph-OPU execution, the computational units are shared between SpMM and GEMM instead of being switched, which improves the hardware utilization. Finally, we implement a hardware prototype on the Xilinx Alveo U50 and test the mainstream GNN models using various datasets. Experimental results show that Graph-OPU achieves up to 1,654x and 63x speedup, as well as up to 5,305x and 422x energy efficiency boosts, compared to implementations on CPU and GPU, respectively. Graph-OPU outperforms state-of-the-art (SOTA) end-to-end overlay accelerators for GNN, reducing latency by an average of 1.36x and improving energy efficiency by 1.41x on average. Moreover, Graph-OPU exhibits an average 1.45x speed improvement in end-to-end latency over the SOTA GNN processor. Graph-OPU represents an

Traditional island-style FPGAs commonly feature 8 LUTs per CLB based on the CB-SB model, which may not effectively capture the complexities of modern commercial FPGAs. In contrast, contemporary commercial FPGA designs have increased the number of LUTs per CLB to enhance performance, reflecting advancements in technology nodes. To address these challenges and reduce the critical path delay, we propose a high-performance routing architecture with 16 LUTs per CLB based on the General Routing Block (GRB) model. This architecture uses multi-LUT structures to explore the performance advantages in nanoscale FPGAs. Our design space exploration demonstrates significant benefits: compared to the traditional 8-LUT routing architecture, the 16-LUT routing architecture reduces the critical path delay by 14.90% and area-delay product by 14.01% respectively.

The routing architecture significantly impacts FPGA performance and area. Traditionally, routing resources are divided into connection blocks (CBs) and switch blocks (SBs) to implement interconnects based on high-fanin multiplexers (MUXes). The number of MUX levels is typically fixed in past studies, resulting in signals traversing a consistent number of MUXes within defined routing blocks. Although there is a lot of research focusing on the routing model, how MUXes implement these connections is less explored. In this paper, we propose a novel routing architecture based on multi-level MUXes, allowing for flexible driving relationships based on connections through various numbers of MUX levels. We define parameters to describe the multi-level MUX architecture, covering the number of MUX levels and the type and number of MUX fan-ins, and conduct experiments to investigate the effectiveness based on these parameters. In addition, we employ Bayesian Optimization (BO) for design space exploration based on the above parameters and wire distribution. The experimental result demonstrates that the optimized multi-level architecture achieves a 13.6 % reduction in critical path delay (CPD) with a 4.3 % overhead in total routing area compared to General Routing Block (GRB) architecture using VTR benchmarks. The multi-level MUX result also surpasses the BO searched result without the exploration of MUX arrangement, showing improvements of 6.9 % in CPD and 2.1 % in total routing area. Additionally, it shows 8.6 % and 5.0% improvement in CPD and routing area respectively than the versatile interconnection block (VIB) architecture.

A few overlay processors for transformer networks emerge to achieve reconfigurable architectures and dynamic instructions. However, these processors consistently neglect exploring network sparsity, while existing sparse accelerators inefficiently utilize resources with separate computation parts. Furthermore, mainstream compilers for instruction generation are intricate and demand significant engineering efforts. In this work, we propose CSTrans-OPU, an FPGA-based overlay processor with full compilation for transformer networks via sparsity exploration. Specifically, we customize a multi-precision processing element (PE) array with DSP-packing for unified computation format with full resource utilization. Additionally, the introduced sorting and computation mode selection modules make it possible to explore the token sparsity. Moreover, equipped with a user-friendly compiler, CSTrans-OPU enables model parsing, operation fusion, model quantization, instruction generation and reordering directly from model files. Experimental results show that CSTrans-OPU achieves 6.92-20.06x speedup and 182.48x higher energy efficiency compared with CPU, and 1.473.85x latency reduction with 4.63-52.53x better energy efficiency compared with GPU. Furthermore, we observe up to 4.28x better latency and 4.94x higher energy efficiency compared with previously customized accelerators, and can be up to 1.93x faster and 4.39x more energy efficient than FPGA processors. To the best of our knowledge, our CSTrans-OPU is the first overlay processor for transformer networks considering sparsity.

Zero-knowledge proof (ZKP) plays a significant role in privacy protection technology. However, the proof generation phase requires considerable time and hardware resources. In this phase, Number Theoretic Transform or Inverse Number Theoretic Transform (NTT/INTT) in polynomial computation, as well as Multiple Scalar Multiplication (MSM), are bottlenecks that dominate the execution time. In this paper, we propose a highly reconfigurable accelerator ReZK to accelerate ZKP proof generation phase, focusing on NTT/INTT and MSM. According to the configurations, ReZK can be configured as NTT, INTT, and MSM with variable sizes and bit-widths by adjusting the data path between on-chip memories and arithmetic cores. As the basic unit of arithmetic cores, the reconfigurable processing element (PE) in ReZK is composed of pipelined modular multipliers and modular adders that support variable bit-widths. It can perform butterfly or arithmetic operations. Based on the reconfigurable PEs, the ReZK core can implement NTT/INTT with different sizes and bit-widths, or a fully pipelined point adder (PADD). Additionally, we propose a modularized MSM scheduling architecture to support various bit-widths. The on-chip memories are also well organized for reuse. In NTT/INTT mode, 4-way 256-bit or 2-way 384-bit NTT/INTT can be computed in parallel. In MSM mode, for different elliptic curves, ReZK is capable of processing 4-way 256-bit or 2-way 384-bit MSM in parallel.

Recently, there has been increased emphasis on privacy-preserving computation technologies such as homomorphic encryption (HE) and Zero-knowledge proof (ZKP). Modular multiplication is a critical component for both HE and ZKP. Variable bit-width is a must for many applications of privacypreserving computation, due to variable bit-width requirements for different cryptography schemes. However, the majority of modular multipliers that support variable bit-width configurations exhibit relatively low throughput. This work presents a fully pipelined Montgomery modular multiplier with variable bitwidth support. Truncated multipliers are introduced to reduce the resources of modular multipliers in our approach. In order to meet different bit-width requirements, the proposed modular multiplier can be dynamically reconfigured. The proposed design can support widely used bit-width configurations, specifically, 384-bit, 256-bit, and 128-bit. 256-bit and 128-bit modes support parallel computation of 2 and 6 sets of operands, respectively. Compared with existing variable bit-width modular multipliers, the proposed reconfigurable modular multiplier significantly improves the throughputs with even lower resources.

Multi-Scalar Multiplication (MSM) is a computationally intensive task that operates on elliptic curves based on GF(P) . It is commonly used in zero-knowledge proof (ZKP), where it accounts for a significant portion of the computation time required for proof generation. In this article, we present PriorMSM, an efficient acceleration architecture for MSM. We propose a Priority-Based Scheduling Mechanism (PBSM) based on a multi-FIFO and multi-bank architecture to accelerate the implementation of MSM. By increasing the pairing success rate of internal points, PBSM reduces the number of bubbles in the pipeline of point addition (PADD), consequently improving the data throughput of the pipeline. We also introduce an advanced parallel bucket aggregation algorithm, leveraging PADD’s fully pipelined characteristics to significantly accelerate the implementation of bucket aggregation. We perform a sensitivity analysis on the crucial parameter of window size in MSM. The results indicate that the window size of the MSM significantly impacts its latency. Area-Time Product (ATP) metric is introduced to guide the selection of the optimal window size, balancing the performance and cost for practical applications of subsequent MSM implementations. PriorMSM is evaluated using the TSMC 28 nm process. It achieves a maximum speedup of 10.9× compared to the previous custom hardware implementations and a maximum speedup of 3.9× compared to the GPU implementations.

Stable Diffusion has become one of the mainstream image synthesis algorithms. The mainstream computing platform for Stable Diffusion is GPU. However, the deployment of Stable Diffusion on GPU still faces the problems of power consumption. With dedicated hardware design and optimization, FPGA based Stable Diffusion accelerator can achieve better performance of energy efficiency. In this paper, we propose SDAcc for realizing efficient inference of Stable Diffusion on FPGA. SDAcc is 4.40x faster than CPU. Compared to GPU and CPU, SDAcc achieves 1.27x and 19.66x energy efficiency improvement, respectively.

Logic synthesis is a crucial step in electronic design automation tools. The rapid developments of reinforcement learning (RL) have enabled the automated exploration of logic synthesis. Existing RL based methods may lead to data inefficiency, and the exploration approaches for FPGA and ASIC technology mapping in recent works lack the flexibility of the learning process. This work proposes ESE, a reinforcement learning based framework to efficiently learn the logic synthesis process. The framework supports the modeling of logic optimization and technology mapping for FPGA and ASIC. The optimization for the execution time of the synthesis script is also considered. For the modeling of FPGA mapping, the logic optimization and technology mapping are combined to be learned in a flexible way. For the modeling of ASIC mapping, the standard cell based optimization and LUT optimization operations are incorporated into the ASIC synthesis flow. To improve the utilization of samples, the Proximal Policy Optimization model is adopted. Furthermore, the framework is enhanced by supporting MIG based synthesis exploration. Experiments show that for FPGA technology mapping on the VTR benchmark, the average LUT-Level-Product and script runtime are improved by more than 18.3% and 12.4% respectively than previous works. For ASIC mapping on the EPFL benchmark, the average Area-Delay-Product is improved by 14.5%.

There are already some works on accelerating transformer networks with field-programmable gate array (FPGA). However, many accelerators focus only on attention computation or suffer from fixed data streams without flexibility. Moreover, their hardware performance is limited without schedule optimization and full use of hardware resources. In this article, we propose a flexible and efficient FPGA-based overlay processor, named FET-OPU. Specifically, we design an overlay architecture for general accelerations of transformer networks. We propose a unique matrix multiplication unit (MMU), which consists of a processing element (PE) array based on modified DSP-packing technology and a FIFO array for data caching and rearrangement. An efficient non-linear function unit (NFU) is also introduced, which can calculate arbitrary single input non-linear functions. We also customize an instruction set for our overlay architecture, dynamically controlling data flows by instructions generated on the software side. In addition, we introduce a two-level compiler and optimize the parallelism and memory allocation schedule. Experimental results show that our FET-OPU achieves 7.33-21.27× speedup and 231× less energy consumption compared with CPU, and 1.56-4.08× latency reduction with 5.85-66.36× less energy consumption compared with GPU. Furthermore, we observe 1.56-8.21× better latency and 5.28-6.24× less energy consumption compared with previously customized FPGA/ASIC accelerators and can be 2.05× faster than NPE with 5.55× less energy consumption.

Reducing the critical path delay is the key to optimizing the circuit performance since it determines the maximum operating frequency. Retiming is a synchronous circuit transformation that can reduce the critical path delay by moving registers across combinational circuit elements. Compared with ASIC, more than 55% physical delays of FPGA come from the interconnection. Hence it is beneficial to use these interconnection delays for FPGA retiming. However, FPGA retiming is normally carried out before or during placement and routing without precise static timing analysis (STA), which leads to inaccurate physical timing optimization results. In addition, it is also a difficult task to verify the functional equivalence of circuits before and after retiming. In this paper, we propose an iterative and verifiable retiming algorithm, which extracts critical path information from the STA report and iteratively performs retiming by modifying BLIF netlist based on the physical interconnection delay, rather than the logic depth. Our experimental results based on VPR benchmark demonstrate that our method can reduce critical path delay by 5% on average while ensuring the functional equivalence. Compared to retiming in ABC, which lacks physical timing information, our method achieves smaller delay with fewer registers used. Compared to Vivado retiming gain on Virtex-7, the proposed method can achieve an 1.3% retiming gain improvement on k6_Frac_N10_Frac_Chain_Mem32K_40nm in VPR.