This paper presents a 16-channel neural recording IC that achieves massive data-rate reduction through a spike-driven adaptive-basis compressive sensing (CS). To address wireless data-rate bottlenecks in high-density recording, a two-stage compression scheme that integrates on-chip spike detection with CS encoding is proposed. The adaptive dictionary learning tracks non-stationary neural signals in real-time, maintaining high reconstruction fidelity even under significant temporal drift. Furthermore, a wide-DR analog front-end ensures robust tolerance to large transient stimulation artifacts. Measured results demonstrate $168 \times$ data-rate reduction with 96.8% classification accuracy, slashing the per-channel datarate to 1.92 kbps, while the CS block consumes only $2.2 \mu \mathrm{W}/\text{ch}$. This enables a highly efficient and scalable interface for artifact-tolerant, long-term implantable neural recording.

Accurate heart rate estimation from single-channel photoplethysmography (PPG) remains challenging in wearable settings because motion artifacts corrupt the pulsatile waveform. Multi-sensor fusion and deep learning approaches mitigate these artifacts but impose additional hardware cost or computational burden unsuitable for resource-constrained edge devices. This paper proposes SMD-NLMS, a lightweight, model-free, sensor-less framework for single-channel PPG-based heart rate estimation during ambulatory motion. A motion-related noise reference is synthesized directly from the input PPG by aggregating delayed replicas using a root-sum-of-squares (RSS) operation, and this intrinsic reference drives a normalized least mean squares (NLMS) adaptive filter to suppress artifacts without auxiliary inertial sensors, and substituting a physical tri-axial accelerometer for it changes the primary-set error by less than 0.3 bpm. Heart rate tracking is stabilized by a maximal rate of heart rate increase (rHRI)-derived bounded search corridor (± 18 bpm) integrated into spectral peak selection, enforcing physiological plausibility without post-smoothing latency. On the IEEE Signal Processing Cup 2015 dataset (22 subjects), SMD-NLMS achieves a mean absolute error (MAE) of 2.43 beats per minute on the 20-subject primary evaluation set—with the full 22-subject MAE of 3.35 bpm also reported for transparency—using approximately 130 multiply-accumulate operations per sample and a sub-kilobyte memory footprint, establishing an accuracy baseline for model-free, sensor-less single-channel PPG estimation while offering substantially lower computational cost and hardware complexity compared with multi-sensor and deep learning alternatives. Transferred without re-tuning to PPG-DaLiA’s daily-living recordings, the same configuration yields 16.55 bpm, bounding the validated envelope to structured, quasi-periodic exercise.

Objective: This paper presents a phase-shifted foursurface capacitive cage architecture that synthesizes a rotating electric field for in-plane orientation-invariant voltage delivery to implant-compatible bare electrodes, eliminating the angular dead zone of conventional two-surface capacitive systems, for headstage-free experiments on freely moving animals. Methods: The four cage walls form two orthogonal transmitter pairs driven with a 90° phase difference, generating a rotating electric field. A differential electrode configuration addresses the floating-ground condition of implants, and a cross-coupled rectifier converts the received signal to DC without a grounded instrument. Validation was ex vivo in porcine tissue at 33 MHz. Results: The rectified DC voltage was 2.00–2.33 V across nine cage regions and 2.0–2.45 V across the measured in-plane rotation angles at three locations, whereas two-surface excitation showed near-zero output at 90°. Voltage varied negligibly over 2–6 cm electrode separation, which the quasi-static model does not predict and lead pickup would explain; multi-subject operation was demonstrated qualitatively. Conclusion: The architecture eliminates in-plane orientation-dependent dead zones under quasi-static cage-based WPT conditions; whether the voltage develops across the in-tissue electrode span or along the leads remains unresolved. Analytical SAR (0.08–0.15 W/kg) and Pennes bioheat analysis (ΔT < 0.1 K) indicate compliance with the 2 W/kg and ISO 14708-1:2014 2 °C limits, and the same restriction caps deliverable power at ≈ 17 mW; these estimates presuppose the unresolved in-tissue coupling path. Significance: This ex vivo proof-of-concept underpins future capacitive WPT systems; transmitter-side efficiency, in vivo validation, and z-axis robustness are reserved for follow-on studies.

We present a 64-channel implantable neural stimulator with sub-nC charge-balanced current stimulation for seizure suppression applications. The regulated cascode current driver achieves almost full VDD compliance voltage range with 98% supply voltage utilization (4.9V from 5V) in standard 0.18 mu m CMOS technology, eliminating the need for expensive high-voltage processes. A passive charge balancing scheme using a bootstrapped switch with reduced on-resistance (19.56 Omega) maintains residual charge levels below 1 nC, well within the 15 nC safe limits, enabling reliable long-term operation. The stimulation parameters, including current pulse width (1 mu s-1023 mu s), channel activation, stimulation frequency, and current amplitude (1 mu A to 1.8 mA), are highly re-configurable through a 10 MHz SPI interface, enabling real-time adaptive stimulation protocols. The hierarchical 8 + 3-bit DAC architecture provides superior current resolution compared to existing single DAC systems while maintaining compact area efficiency of 0.0125 mm2 per channel. In-vivo animal experiments demonstrate effective seizure suppression, achieving seizure reduction within 14 seconds after 40 seconds of 5 Hz stimulation at 50 mu A amplitude, validating the therapeutic efficacy of the proposed system. The fabricated IC in 0.18 mu m standard CMOS process successfully combines high channel count, optimal compliance voltage utilization, enhanced safety margins, and in-vivo validation, making it suitable for practical implantable epilepsy treatment applications.

This paper presents an implantable cardiovascular biopotential acquisition and stimulation circuit with body-channel (BC) data communication and power transfer capabilities for a transcatheter leadless pacemaker. The power and size requirements of leadless pacemakers, specifically for implantable electronics and minimally-invasive transcatheter delivery, are highly challenging. To reduce size, electrocardiogram (ECG) sensing, pacing, timing and control logic, and body- coupled wireless transceivers are integrated into a single chip. The ECG sensing channel is designed using a current-reused current-feedback instrumentation amplifier to reduce power consumption. The pacing circuit is implemented using a switched-capacitor stimulator with passive discharge for high stimulation efficiency. The pacemaker utilizes BC communication instead of RF communication to achieve low power consumption. The measured input-referred noise of the sensing channel is 3.69 μVRMS, and the power consumption ranges from 4.5 to 19.4 μW. The downlink and uplink speeds of BC communication are 10 Mbps and 16 kbps, respectively. The internal rechargeable battery is properly charged when a 600 mVPP, 20 MHz input signal is applied. The leadless pacemaker prototype is implemented with a small size of 5.89 mm and 26.5 mm in diameter and length, respectively. The performance of the leadless pacemaker prototype is evaluated through in vivo experiments using swine.

This paper presents a wireless biphasic neurostimulator that exploits body-coupled powering and full-duplex communication, achieving precise stimulation with real-time feedback. Simultaneous wireless power and data transmission can be achieved with a baseband load shift keying. A fully balanced biphasic stimulation can be achieved, whose current is applied using flying capacitors and current regulators, and the residual charge after biphasic stimulation becomes extremely small. Implemented in a 65 nm CMOS, the prototype IC achieves a downlink BER of $1.8 \times 10^{-4}$, an uplink BER of $< 3 \times 10^{-5}$, and a residual charge of 0.22 nC at a depth of 40 mm in porcine tissue.

This paper presents an LNA-embedded CT $\Delta\Sigma$ ADC for closed-loop neural recording. The frontend LNA is embedded in the loop filter of $\Delta\Sigma$ ADC to achieve low input-referred noise (IRN) and high tolerance to stimulation artifacts. A 25-level feedback RDAC is realized with a 12-tap tri-level FIR-DAC and helps to linearize the LNA, resulting in high linearity over a wide input range. The FIR-DAC's delay is compensated by a novel feedforward compensation scheme to maintain loop stability. The DC-coupled LNA is chopped at a low frequency (~100kHz) and provides high input impedance, low offset, and low $1/f$ noise without suffering from chopper artifacts. Implemented in a 65nm CMOS process, the ADC achieves an IRN of 62.5nV/√Hz, 86.7dB SNDR, 87.5dB DR, and 97.9dB SFDR, while consuming only $11.8\mu \mathrm{W}$ in a 10kHz bandwidth. This corresponds to the state-of-the-art FoM of 176.8dB.

We introduce a highly efficient 48-channel ultrasound beamforming system ideal for ultrasound endoscopy applications. The system includes a transmitter and a receiver that allows for low-area, high-resolution imaging acquisition. The transmitter uses a charge redistribution HV (high-voltage) scheme to generate three-level pulses that actuate the transducer, implemented with the standard CMOS process for optimal cost and power savings. Meanwhile, the receiver features a sub-array structure and a delay generator that reduces the area usage. To achieve high-resolution ultrasound imaging acquisition with low computational power, we developed a Shift Coherence Factor (SCF) algorithm that is hardware-friendly. This approach delivers a lateral resolution of over 20% better than that of the conventional delay and sum (DAS) algorithm, with a contrast ratio of over 30 dB. The system was implemented in a 180 nm standard CMOS process with an area of 24.98 mm2, power consumption of 8.23 mW per channel, achieving a delay resolution of 8.33 ns, and a low-area implementation of 0.52 mm2 per channel. The system offers high-quality imaging acquisition with minimal additional area and power consumption, which has great potential for 3D imaging or catheterized ultrasound systems.

This paper presents a wireless neurostimulator for multisite stimulation in freely behaving animals. The neurostimulator IC is wirelessly powered via a 16MHz body-coupled link, and controlled by forward telemetry, which provides stimulation parameters via amplitude shift keying (ASK) modulation. It can provide various stimulation protocols with a maximum current of $225\mu \mathrm{A}$ , achieving the highest end-to-end efficiency of 1.72% at a TX/RX distance of 10cm. Moreover, multisite stimulation is fully validated through in vivo experiments.

This paper presents a highly efficient, low-power, compact mixed-signal sinusoidal current generator (CG) integrated circuit (IC) designed for bioelectrical impedance spectroscopy (BIS) with low total harmonic distortion (THD). The proposed system employs a 9-bit sine wave lookup table (LUT) which is simplified to a 4-bit data stream through a third-order digital delta–sigma modulator (ΔΣM). Unlike conventional analog low-pass filters (LPF), which statically limit bandwidth, the finite impulse response (FIR) filter attenuates high-frequency noise according to the operating frequency, allowing the frequency range of the sinusoidal signal to vary. Additionally, the output of the FIR filter is applied to a 6-bit capacitive digital-to-analog converter (CDAC) with data-weighted averaging (DWA), enabling dynamic capacitor matching and seamless interfacing. The sinusoidal CG IC, fabricated using a 65 nm CMOS process, produces a 5 μA amplitude and operates over a wide frequency range of 0.6 to 20 kHz. This highly synthesizable CG achieves a THD of 0.04%, consumes 19.2 μW of power, and occupies an area of 0.0798 mm2. These attributes make the CG IC highly suitable for compact, low-power bio-impedance applications.

This paper demonstrates body-coupled (BC) data transmission and multi-source power delivery systems for neural interface applications. The implanted data transmitter and power receiver utilize an electrode interface rather than an antenna or coil interface for battery-free wireless transmission, enabling the external data receiver and power transmitter with patch electrodes to be placed away from the implant without requiring precise alignment, which is a critical issue in the conventional communication modalities of inductive coupling. Significantly, the implanted power receiver produces the supply voltage using ambient body-coupled 50/60 Hz signals from the Mains, on top of the 40.68 MHz wireless power source from the external power transmitter, to increase the recovered power level and the voltage conversion efficiency (VCE). The body-coupled wireless systems for implanted and external devices are implemented with integrated circuits (ICs) fabricated in a 180 nm CMOS process. When 650 mVpp AC voltage is applied to the implanted device, the power receiver recovers up to 780 μW with ambient (60 Hz signals) BC energy harvesting, achieving 93% VCE, while 600 μW is recovered without ambient (60 Hz signals) signal. The recovered power supplies the regulated voltage to the direct-digital signaling transceiver, which consumes 460 μW with an uplink data rate of 10 Mbps and a downlink data rate of 200 kbps, corresponding to an energy efficiency of 46 pJ/b.

We present a 64-channel implantable neural stimulator with sub-nC charge balanced current stimulation for seizure suppression applications. The regulated cascode current driver achieves almost full VDD compliance voltage range. A passive charge balancing by shorting working and reference electrodes with a bootstrapped switch keeps the residual charge level within a safe limit, enabling faster-switching operation. The stimulation parameters, such as current pulse width, channel activation, activation frequency, and current amplitude, are highly reconfigurable and adjusted through the SPI interface. Significantly, the current amplitude can be varied from 1μA to 1.8 mA. As a result, the proposed neural stimulator fabricated with a 0.18μm standard CMOS process effectively suppresses seizures within a safe limit with a residual charge of less than 1nC through the in-vivo test.

Abstract This paper presents 2‐channel time‐multiplexed chopper instrument amplifier for better gain accuracy and mismatch. Mostly, the current‐attenuated feedback resistor with a duty‐cycled resistor is adopted for boosting the RC time constant. It can achieve the high pass corner frequencies between 10 Hz and 320 Hz by a 3‐bit digitally controlled resistor bank of the attenuator. As a result, the instrument amplifier achieves 0.6% gain accuracy between two time‐multiplexed channels, 100 dB CMRR, ‐40 dB crosstalk, and noise densities of 50nV/√Hz. It is implemented in a 180‐nm CMOS technology. It occupies a 0.6 mm*0.6 mm chip area and consumes 1.5μA current consumption from a 1.8 V supply for each channel.

This article presents a wireless neural implant with body-coupled (BC) data transmission and power delivery for freely behaving animals and incorporates a precision front end for high-quality neural recordings. The neural implant utilizes the body as a wireless transmission medium where it only needs small electrodes for data transmission and power delivery. An external device with patch electrodes can then be placed far away from the implant without the need for precise alignment. Furthermore, a four-channel continuous-time delta–sigma modulator (CT- $\Delta \Sigma \text{M}$ ) is integrated into the system for precision neural recordings. Each neural recording CT- $\Delta \Sigma \text{M}$ achieves an 82.3-dB signal-to-noise and distortion ratio (SNDR) and an 83.3-dB dynamic range (DR) while consuming only 8.6- $\mu \text{W}$ at a signal bandwidth of 10 kHz. The neural implant integrated circuit (IC) is fabricated in a 0.11- $\mu \text{m}$ CMOS with a high-density capacitor option, and the BC data receiver (RX) IC is implemented in a 0.18- $\mu \text{m}$ CMOS. The implant IC occupies a chip area of 4 $\text {mm}^{2}$ , including a 5-nF on-chip capacitor, and draws 280 $\mu \text{A}$ from a 2.3-V supply with a working data transmitter (TX) electrode. By exploiting direct-digital signaling for data transmission, the neural implant achieves a data rate of 20.48 Mb/s and a wireless power recovery of 644 $\mu \text{W}$ , resulting in an energy efficiency of 32 pJ/b. The entire neural implant system has been successfully verified by both electrical and in vivo measurements, while the wirelessly recorded electrocorticography (ECoG) signals with the prototype neural implant inside a rat demonstrate the end-to-end functionality of the proposed system.

In this letter, the authors present a high-efficiency AC-to-DC rectifier for a wireless power transmission system with an internal threshold voltage cancellation (IVC) scheme to improve power conversion efficiency (PCE) and voltage conversion ratio (VCR). The rectifier with the IVC scheme implemented in 0.18-μm CMOS technology achieves a power efficiency of 86% at a resistive load of 510 Ω when a 13.56-MHz AC signal with a 6-V amplitude is applied. In contrast, a previous scheme shows a 58% PCE under the same condition.

We present a low-power area-efficient subarray beamforming receiver (RX) structure for a miniaturized 3-D ultrasound imaging system. Given that the delay-and-sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog-to-digital converter (ADC) shares its capacitive digital-to-analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power-hungry ADC buffers. Furthermore, the dual reference 10-bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.

Miniaturized neural implants for monitoring neurological disorders have been investigated as a promising alternative to the neural interface for patients. However, such implants rely on physical tethers to external hardware for data and power transmission, which not only causes tissue damage and infection, but also hinders stable in vivo recordings in freely behaving animals. To enable non-tethered implants, a key feature for the robust and high-fidelity neural interface, neural implants using various wireless technologies have been reported (Fig. 20.5.1, top-left) [1]–[3]. However, the use of an inductive link [1] imposes a stringent requirement on the alignment between coils, as well as a limited transfer range. Optical [2] and ultrasound [3] telemetry suffer from attenuation from skull absorption, which requires surgically placed sub-cranial repeater or has only been demonstrated at low data rates (tens of kb/s). Hence, they are limited to the short operation range and the susceptibility to orientation, and in most cases still need a headstage that restricts freedom of action.

This paper presents a driver status monitoring (DSM) system with body channel communication (BCC) technology to acquire the driver's physiological condition. Specifically, a conductive thread, the receiving electrode, is sewn to the surface of the seat so that the acquired signal can be continuously detected. As a signal transmission medium, body channel characteristics using the conductive thread electrode were investigated according to the driver's pose and the material of the driver's pants. Based on this, a BCC transceiver was implemented using an analog frequency modulation (FM) scheme to minimize the additional circuitry and system cost. We analyzed the heart rate variability (HRV) from the driver's electrocardiogram (ECG) and displayed the heart rate and Root Mean Square of Successive Differences (RMSSD) values together with the ECG waveform in real-time. A prototype of the DSM system with commercial-off-the-shelf (COTS) technology was implemented and tested. We verified that the proposed approach was robust to the driver's movements, showing the feasibility and validity of the DSM with BCC technology using a conductive thread electrode.

AbstractThe authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog‐to‐digital converter (ADC) shares its capacitive digital‐to‐analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power‐hungry ADC buffers. Furthermore, the dual reference 10‐bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.

The natural compound eye system has many outstanding properties, such as a more compact size, wider-angle view, better capacity to detect moving objects, and higher sensitivity to light intensity, compared to that of a single-aperture vision system. Thanks to the development of micro- and nano-fabrication techniques, many artificial compound eye imaging systems have been studied and fabricated to inherit fascinating optical features of the natural compound eye. This paper provides a review of artificial compound eye imaging systems. This review begins by introducing the principle of the natural compound eye, and then, the analysis of two types of artificial compound eye systems. We equally present the applications of the artificial compound eye imaging systems. Finally, we suggest our outlooks about the artificial compound eye imaging system.