This paper presents SR-VLNA, an energy-efficient spatial reasoning-based vision language navigation (VLN) accelerator. The spatial reasoning consists of 1) 3D Gaussian splattingbased semantic understanding (SU), and 2) language-based planning (LP). SR-VLNA proposes 4 features of ESU, MRDU, CAGQU, and HSAT and reduces energy of SU and LP by $7.0 \times$ and $10.9 \times$, respectively. Fabricated in 28 nm FDSOI, SRVLNA achieves state-of-the-art SU performance at 0.004 $0.021 \mu ~\mathrm{J} /$ point and is the first to demonstrate LP with $0.25-0.96 \text{mJ} /$ task. Finally, SR-VLNA demonstrates end-to-end VLN system with $5.0-23.9 ~\text{mJ} /$ meter.

This paper presents NOVA, the first fully integrated neural video system-on-chip (SoC) for end-to-end decoding-processing-encoding on a single chip. A bound-guided mixed quantization (BMQ) and bound-guided unified (BU) core achieves 41.7% computation power reduction. A temporal interpolation unit (TIU) with tiered direct memory access (DMA) reduces system energy by 71.8%. An adaptive entropy coding unit (AECU) reduces coding latency by 79.2%. NOVA is fabricated in 28nm CMOS technology and achieves 31.4 TOPS/W energy efficiency on 4K UVG benchmark.

SMoLPU is an energy-efficient MoE-based speculative decoding LLM processor with an NPU-CIM core. It has 3 features: 1) Token-adaptive expert refinement removes redundant expert activations and schedules expert load order, achieving 2.3x/4.2x energy efficiency improvement in prefill/decode; 2) An adaptive-offload NPU-CIM core and a top scheduling unit maintain HW utilization under dynamic INT-FP ratios, achieving 3.3x lower latency; 3) A reconfigurable DRAM-based LUT-CIM reduces adder tree power/area, while supporting dynamic input size. The LLM processor achieves 43.5% lower energy per parameter than prior SOTA.

This paper presents a real-time and energy-efficient 3D Gaussian Splatting (3DGS)-based geometric and semantic mapping processor for embodied agents. The proposed processor exploits two levels of redundancy: 1) Embedding Redundancy Handling Unit (ERHU), which skips occluded-object embeddings and prunes low-importance channels to reduce 65.6% computation and 77.7% memory access, and 2) Temporal Redundancy Handling Unit (TRHU), which restricts mapping regions to moved objects using bounding-boxes, reducing 93.4% mapping latency. Fabricated in 28nm FDSOI, the processor achieves 70.7 FPS at 0.02 μJ/point for 640×480 dense semantic mapping.

Reasoning strategies such as chain-of-thought improve the accuracy of large language models (LLMs) but lengthen decoding sequences, inflating external memory access (EMA) on mobile devices. Numerous optimizations have been explored to reduce EMA, from conventional techniques such as group quantization and channel-wise pruning to sparse mixture-of-experts (MoE) and speculative decoding (SD). By holistically adopting these techniques, up to 89.7% EMA energy reduction can be achieved. However, group quantization with channel-wise pruning reduces intra-group INT MACs while increasing the proportion of inter-group FP MACs, creating distinct heterogeneous INT-FP workloads. NPU-CIM architectures, which process INT MACs on energy-efficient CIM and FP MACs on a flexible NPU, are well-suited for this workload. Nevertheless, conventional NPU-CIM fails to fully exploit MoE-based SD due to redundant expert activation, low hardware utilization from dynamic and heterogeneous workloads, and high power consumption in CIM. We present SMoLPU, a pipelined NPU-CIM architecture for energy-efficient MoE-based SD LLM inference on mobile devices with three key features. Token-adaptive expert refinement (TaER) eliminates redundant expert fetching and schedules the expert load order, achieving $2.3\times $ and $4.2\times $ energy efficiency improvements in the prefill and decode stages. An adaptive-offload NPU-CIM core (ANC) maintains high utilization under dynamically varying INT-FP ratios by bundling dense groups for CIM and offloading sparse groups to idle NPU, achieving a $3.3\times $ end-to-end speedup. Reconfigurable DRAM-based LUT-CIM enables low-power addition while supporting variable input sizes, reducing adder tree power and area by 36.8% and 26.3%. SMoLPU is fabricated in a 28-nm CMOS technology and occupies 20.25 mm2. It achieves 7.8 fJ/token/parameter, which is 43.5% lower energy per parameter than the state-of-the-art.

This work introduces SLYTHERIN, a redundancy-conscious accelerator design that exposes and eliminates structural redundancy inherent in state-space model (SSM)-based video inference. Recent video models have increasingly adopted SSM to replace attention mechanisms, enabling linear time and space complexity in sequence length, well-suited for long-range video understanding. However, despite its algorithmic efficiency, its deployment on resource-constrained platforms remains challenging due to (1) slow inference latency caused by sequential SSM operations and (2) excessive energy consumption dominated by frequent external memory access (EMA), particularly for high-resolution, long-duration video streams. SSM-based video inference inherently exhibits multiple forms of structural redundancy stemming from sequential state updates and spatio-temporal input characteristics. To address these redundancies, SLYTHERIN instantiates three architectural mechanisms that jointly optimize computation and memory access. First, an orchestrated task allocator eliminates token-level redundancy by identifying and removing redundant and low-importance tokens through input-adaptive token selection. Second, a reformulated SSM core removes state update redundancy by reordering SSM operations and applying fixed-size block processing, enabling localized state updates with reduced memory traffic. Third, a patch data management unit mitigates EMA energy through difference-based bit-sliced compression that exploits inter-frame locality. Consequently, SLYTHERIN achieves 2.81 mJ/frame energy consumption while maintaining real-time performance at 275 FPS.

This paper proposes a HW/SW Co-Optimized OnLine 3D Gaussian Splatting modeling accelerator, COOL-splat, for real-time AR/VR applications on mobile devices. To address high external memory access energy and redundancies in computation, COOL-splat introduces novel contributions across SW, core, and PE levels. Projected gradient interpolation-based masked training (SW), bi-directional rendering core (Core), and reconfigurable gaussian computation units supporting mixed-precision (PE). These enhancements achieve an average modeling efficiency of 10.1 mJ/iter, outperforming state-of-the-art processors by 1.49×.

Token merging is a widely adopted technique in vision transformers (ViTs) to reduce computation with minimal accuracy degradation. However, in tasks that require fine-grained outputs, such as text-unified object recognition, aggressive merging reaches a limit due to accuracy loss. To address this, we introduce a method that exploits residual token similarity beyond the merging threshold using difference computing, which significantly improves energy efficiency. The proposed processor integrates the post merging residual difference (PMRD) algorithm, which first reduces 34% of tokens through merging, then applies difference computing to the remaining tokens. This results in a 31% reduction in effective bit operations by leveraging residual similarity. To further exploit the resulting bit-level sparsity, the processor employs sparsity-separated accumulation with sign-magnitude representation (SSA-SM) and a bi-directional dynamic memory allocation (BDA) to optimize both computation and memory access. These enhancements yield an additional 29.4% computational energy savings. Overall, the system achieves a 2.22x improvement in energy efficiency and delivers 7.23 TOPS/W on the MS COCO dataset for text-unified object recognition.

This brief proposes a high-efficiency spiking neural network (SNN) processor for point-cloud neural network (PNN) based 3D object recognition on edge devices. PNN independently process points, leading to redundant computations and low energy efficiency. SNN leverage the characteristics of accumulation operations and the properties of Leaky Integrate-and-Fire (LIF) activation, to optimize efficiency. A novel 3D object recognition processor maximizes the characteristics of SNN by introducing two key features: 1) intra-timestep computation skipping and 2) timestep reduction via inter-timestep correlation analysis. The Event-driven Bit-serial Processing Unit (EBPU) utilizes intra-timestep computation skipping for up to 7.2x higher energy-efficiency. The Output Spike Precognition Unit (OSPU) enhances inter-timestep correlation analysis for 65% improvement in throughput. Consequently, the proposed processor achieves an energy efficiency of 227.1 TOPS/W for 3D object classification, 218.1 TOPS/W for part segmentation, and 92.5 TOPS/W for semantic segmentation, achieving up to 22.9x higher energy efficiency than the conventional state-of-the-art PNN accelerators.

This paper presents DIAL, an energy-efficient DRAM inmemory computing accelerator with partial product LUTbased architecture for advanced tasks. The compact LUT reduces 53% of the LUT area and 45% of power by eliminating extended zeros. The twisted differential ADC reduces ADC area by 37 % and power by 45 % through comparators sharing and improves CSNR by using a 2.3fF computation capacitor and increasing ADC resolution by $3 \times$. The dual-mode sense amplifier reduces 33% of LUT power by adjusting operation modes based on data patterns. Fabricated in 28 nm CMOS technology, DIAL occupies a $20.25 \text{mm}^{2}$ die area and achieves 55.4 TFLOPS/W energy efficiency on the GPT-2 benchmark, demonstrating a $4.1 \times$ higher efficiency than prior IMC designs.

This work presents an energy-efficient and real-time rendering Neural-3DGS processor for mobile AR/VR devices. While Neural-3DGS shows high-quality and fast rendering, it exhibits low energy efficiency & high latency in mobile implementation. The proposed processor has three key features for the overall processes in Neural-3DGS: 1) Voxel Similarity-aware Memory Management Unit (VSMMU) eliminates redundant operations and achieves 59.5%, 43.3% reduced energy for external memory access and neural-network computation. 2) LUT-based Pre-Sort Unit (LPSU) utilizes pre-computed order to reduce the latency of sorting by 64.3%. 3) Opacity-aware Gaussian Skipping Core (OGSC) exploits sparsity based on opacity and process 63.3% reduced MAC operations. The proposed processor is implemented in 28 nm CMOS technology. It achieves 98.8 FPS for real-time rendering and 4.31 mJ/Frame energy efficiency.

This work presents a real-time 3D Gaussian Splatting-based SLAM (3DGS-SLAM) accelerator to support high-quality dense mapping in mobile environments. There are two main hardware challenges for 3DGS-SLAM acceleration; 1) Large power consumption due to non-uniform memory access and 2) Excessive a-computation caused by processing unnecessary pixels. To solve these issues, two key building blocks are integrated in the proposed 3DGS-SLAM accelerator. First, a Voxel-based Gaussian Management (VGM) divides the entire scene into multiple voxels enabling selective Gaussian fetching with streaming off-chip memory access. This method reduces external memory access by 26.2%. Second, ROI-based Pixel-wise Skipping (RPS) reduces 68.3 % of a-computation by skipping unnecessary pixels outside of ROI. As a result, the proposed 3DGS-SLAM accelerator is implemented on Intel's Cyclone V with a maximum clock frequency of 200 MHz. Evaluating on Replica dataset, it achieves 15.2 FPS 3DGS-SLAM enabling highquality dense mapping on mobile devices.

This paper presents NuVPU, a unified neural video processor that supports both streaming and post-processing with $4.8 \sim 9.6 \text{mJ} /$ frame of energy efficiency. The Selective Convolution-mode Neural Engine (SCNE) adaptively selects either space or NTT convolution domain to increase throughput by $1.69 \sim 3.35 \times$. A Progressive NTT Unit (PNTU) lowers computation by 44.8 % and memory overheads by 80 % during domain changes. A Frequency-aware Compressor (FAC) and Adaptive Tile Scheduler (ATS) reduce the external memory access (EMA) of warping-based frame reuse by 81.3 %. NuVPU in 28nm CMOS process achieves \36.9 TOPS/W on UVG benchmark which is $9.2 \sim 2.3 \times$ higher than previous video processors.

Rapid advancements in neural rendering have revolutionized the fields of augmented reality (AR) and virtual reality (VR) by enabling photorealistic 3D modeling and rendering. However, deploying neural rendering on edge devices presents significant challenges due to computational complexity, memory inefficiencies, and energy constraints. This paper provides a comprehensive overview of neural rendering accelerators, identifying the major hardware inefficiencies across sampling, positional encoding, and multi-layer perception (MLP) stages. We explore hardware-software co-optimization techniques that address these challenges and provide a summary for in-depth analysis. Additionally, emerging trends like 3D Gaussian Splatting (3DGS) and hybrid rendering approaches are briefly introduced, highlighting their potential to improve rendering quality and efficiency. By presenting a unified analysis of challenges, solutions, and future directions, this work aims to guide the development of next-generation neural rendering accelerators, especially for resource-constrained environments.

An implicit neural representation (INR) continuously encodes a 3-D space using a neural network. Neural radiance field (NeRF), a type of INR, achieves a high path planning success rate of 98.6%. It leverages the continuous space representation ability of NeRF. However, accelerating NeRF path planning on edge devices faces limitations due to the excessive computational load. In this article, we present NeRF-Navi, an accurate and energy-efficient 3-D NeRF path planning processor with three key features: 1) dual-attention neural path sampling (DANPS) engine uses map and collision attention to reduce the number of redundant batches, which saves 96.2% of system energy; 2) approximate-accurate (A(2)) core with an error-compensable reduction tree (ECRT) introduces three approximate computing modes with less than 1.6% accuracy overhead; bit sparsity boosting logic (BSBL) increases bit sparsity and reduces the compensation overhead of ECRT; and the A(2) core and BSBL achieve a 26.2% reduction in total system energy; and 3) outlier channel bit-offloading core and bit allocator (BA) that offload sparse MSB bits of outlier channels, reducing total system energy by 36%. NeRF-Navi is fabricated in a 28-nm logic CMOS process and occupies a 6.48-mm(2) die area. NeRF-Navi finally achieves 1.2-8.8x lower path planning energy per task and 1.7-124x lower EDP than the previous 3-D path planning processor.

As artificial intelligence (AI) advances, 3-D spatial computing has emerged as a key application in various fields. It interprets the 3-D space surrounding users and provides them with useful information. This article presents a survey of AI hardware architectures and silicon solutions for 3-D spatial computing systems. The survey categorizes five domains: 1) 3-D data capturing; 2) 3-D data analysis; 3) 3-D hand motion analysis; 4) simultaneous localization and mapping (SLAM); and 5) 3-D rendering. Each session analyzes design considerations for domain-specific accelerators. Finally, this article discusses a next-generation 3-D spatial computing platform that integrates various functions of 3-D spatial computing systems using AI technologies.

An energy-efficient video understanding processor, SLYTHERIN, is proposed to accelerate the new AI model, mamba, efficiently on edge devices. Mamba, a state-of-the-art model for in-context learning, is designed to replace the transformer, whose computational complexity increases significantly in video applications. However, the acceleration of video mamba on edge devices presents two main challenges: 1) slow inference due to the iterative operation phase of mamba and 2) the large energy consumption caused by external memory access (EMA). To address these challenges, the SLYTHERIN is proposed with 3 key building blocks. 1) A 6-stage pipelined task allocator minimizes computational complexity by dynamically managing redundant computations with importance-aware prediction. 2) Reformed computing SSM engine increases core efficiency by tackling the overheads in mamba’s iterative stages with reordering and distributed L1 cache. 3) Patch data management unit addresses the large EMA with difference-based bit-sliced data compression. It finally achieves 2.67-mJ/frame system energy efficiency with 274 FPS.

3D scene reconstruction is a key enabler for emerging mobile applications such as augmented/virtual reality [1]. 3D Gaussian Splatting (3DGS) [2] has emerged as a promising solution for 3D scene reconstruction. Fig. 1 shows three main processes of 3DGS modeling. A scene is composed of multiple distinct 3D gaussians, each having attributes of scales, rotations, RGB color, and opacity. During the pre-processing stage, 3D gaussians are projected onto 2D image plane. In the subsequent volume rendering (VR) stage, alpha values indicating the transparency of each gaussian are computed along a ray originating from each pixel. Then, multiply-and-accumulate operation between alpha and RGB values determines the color of corresponding pixel. In backpropagation (BP), each gaussian’s gradients are computed backward along a ray. Finally, 3D gaussians are updated based on the computed gradients. 3DGS offers higher rendering quality with fewer training iterations compared to neural radiance fields [3]. However, 3DGS faces challenges in achieving low energy and low latency on mobile devices. Power consumption and latency for modeling 3DGS on an edge GPU [4] exceed the requirements by 3.9 times and 7.0 times, respectively [5, 6]. According to the energy and latency breakdown, VR accounts for 62.9% of total modeling energy and 68.8% of total latency. There are two main challenges to solve the bottleneck of VR. First, duplicated gaussians during VR causes large external memory access (EMA) energy. The number of duplicated gaussians is 5.7 times higher than the original, leading to excessive EMA energy which comprises 73.9% of total VR energy consumption. Second, bit redundancy in the VR stage reduces throughput and results in waste of computation energy. The required bit width in VR varies depending on the distance between each gaussian and image plane. This paper proposes Garnet, an energy-efficient 3DGS modeling accelerator featuring 3 key innovations to address these challenges. First, it reduces duplicated gaussians via projected gradient-based pixel skipping. Second, feed-forward (FF) and BP pipeline fusion to reduce latency and redundant memory access. Finally, exploiting approximation and adaptive quantization to remove redundancies. These innovations enable energy-efficient, low latency on-device 3DGS modeling.

This work presents a high-speed 3D Gaussian Splatting-based SLAM (3DGS-SLAM) accelerator to support dense mapping for mobile devices. 3DGS-SLAM has two main hardware challenges for acceleration: 1) Large alpha-computation computation. 2) Memory bottleneck caused by irregular memory access and large number of Gaussians. First, diagonal feeding (DF) controller precludes redundant-alpha computation, and symmetric alpha reuse (SAR) enables reusing computed alpha. This method reduces 35.3% system computation. Second, voxel-based inter-frame caching (VIFC) enables selective inter-frame voxel caching, which reduces 44.0% of external memory access. As a result, the proposed 3DGS-SLAM accelerator achieves 51.2 fps with 0.07 mu J/point with support voltage 0.9V, clock frequency 200MHz mapping a high-quality dense-map.