This paper presents a 3T2C embedded DRAM (eDRAM)-based charge-domain compute-in-memory (CIM) macro for ternary deep feedforward sequential memory network (DFSMN)-based keyword spotting (KWS) with ternary activations and binary weights. The proposed architecture integrates a charge-domain ternary multiply-and-accumulate (MAC) bitcell, a selectable dual-mode sensing scheme, and an in-array offset calibration technique using fixed calibration rows. The dual-mode sensing scheme supports an energy-prioritized conventional sense amplifier (SA) mode for always-on monitoring and an accuracy-prioritized two-step sense amplifier (TSSA) mode for robust inference under reduced sensing margins. The proposed TSSA mitigates decision-timing-induced kickback disturbance, while the calibration rows suppress systematic column-wise sensing offsets. Asense amplifier-based 1-bit readout is employed to minimize area overhead. Fabricated in a 65-nm CMOS process, the proposed macro operates up to 250MHz and achieves 930–1335TOPS/W in the conventional SA mode and 82–336TOPS/W in the TSSA mode, with an area efficiency of 18.45 TOPS/mm2. For DFSMN-based KWS, the measured accuracies with the calibrated TSSA mode reach 91.66%, 89.87%, and 87.30% for the 12-, 20-, and 35-class KWS settings (CLS12, CLS20, and CLS35), respectively. Additional evaluations achieve 98.02% on MNIST and 87.32% on CIFAR-10 with ResNet18, demonstrating the general applicability of the proposed eDRAM CIM macro.

Hybrid Vision Transformers (HybridViTs), which integrate convolutional neural networks (CNNs) with Transformer blocks, offer both local and global feature extraction capabilities, achieving high performance across a range of computer vision tasks. However, the substantial computational asymmetry between lightweight CNN blocks and compute-intensive Transformer blocks presents significant challenges for simultaneous optimization and acceleration within a single hardware architecture. To address these challenges, we propose FLASH, a power-efficient field-programmable gate array (FPGA)-based accelerator tailored for CNN-Transformer hybrid networks. FLASH reduces quantization overhead by consolidating redundant quantization-dequantization operations into a single requantization step and enables 8-bit integer-only computation for residual connections through proper scaling factor handling. To further optimize for hardware efficiency, FLASH introduces hardware-friendly linear approximations of nonlinear functions such as Swish and Softmax. By precomputing row-wise max values through offline calibration, we eliminate both max-value search logic and intermediate memory buffering overhead, while reusing shared integer-exponential units to minimize resource consumption. Architecturally, FLASH employs a two-stage pipeline: Stage 1 eliminates external DRAM access using a fully pipelined MobileNetV2 backbone, while Stage 2 accelerates Transformer and convolutional components through specialized compute units and dataflow optimizations. Experimental evaluation using MobileViT (MViT)-xxs on Xilinx VCU118 FPGA demonstrates that FLASH incurs only a 0.84% accuracy drop on ImageNet-1K compared to the FP32 baseline, while achieving up to $16.8\times $ lower power consumption and $26.3\times $ improvement in energy efficiency relative to CPU/GPU implementations. These results establish FLASH as an energy-efficient hardware accelerator for real-time inference of HybridViT models on edge devices.

Large language models (LLMs) have demonstrated remarkable performance across a wide range of domains. However, their deployment in real-world environments remains challenging due to the substantial model sizes and limited hardware resources. Quantization has been widely adopted to alleviate these issues, but the presence of outliers in the weight distribution of LLMs significantly degrades quantization performance, particularly in low-bit settings. To address this challenge, we propose a region-adaptive non-uniform quantization (RANQ) method that takes into account the intrinsic characteristics of LLM weight distributions. RANQ divides the entire weight space into central and outlier regions, applying distinct scale factors to each region to minimize performance degradation caused by quantization. Furthermore, we introduce a layer-wise reconstruction-based threshold optimization algorithm, which adaptively determines the optimal region boundaries according to the distributional properties of each layer, enabling more precise low-bit quantization. Experimental results on the LLaMA family using the WikiText2 and C4 datasets demonstrate that the proposed method consistently outperforms existing post training quantization (PTQ) techniques, such as round-to-nearest (RTN) and GPTQ.

With the increasing demand for personalized models and the growing emphasis on privacy preservation, efficient training of convolutional neural networks (CNNs) in on-device environments has become a critical challenge. In particular, low-bit quantization during the backward propagation (BP) process is essential due to the substantial computational and memory access demands. However, conventional quantization techniques struggle with the high variability of gradient distributions, leading to significant performance degradation in gradient quantization. To address this issue, we propose a novel hardware-efficient INT8 training framework that is robust against gradient quantization errors. Specifically, we introduce an adaptive multi-scale gradient quantization (AMGQ) method that leverages the inherent characteristics of gradient distributions—typically concentrated around zero yet spanning a broad range—to facilitate effective low-bit training. By selectively processing a subset of the gradient, our approach effectively differentiates between small- and large-magnitude gradient regions, thereby reducing computational overhead while achieving average performance improvements of 0.27% and 0.36% on the CIFAR-10 and ImageNet datasets, respectively, compared to the baseline (i.e., FP32). Furthermore, to mitigate the substantial computational and memory overhead associated with stochastic rounding (SR) in low-bit training, we introduce a flexible linear feedback shift register (LFSR)-based stochastic rounding unit (FlexSRU). FlexSRU employs an LFSR-based approach to efficiently generate random numbers while maximizing randomness through a hierarchical seed generator. Simultaneously, it significantly reduces hardware complexity by reusing random numbers at both the batch and channel levels. Additionally, it extends the period of conventional LFSRs using only bitwise inversion and dynamically adjusts the feedback polynomial to enhance pattern diversity, thereby improving numerical stability. By overcoming the limitations of existing LFSR-based random number generators, our approach enables efficient and precise SR with minimal hardware overhead, making it a promising solution for low-bit CNN training in resource-constrained environments. Consequently, the proposed framework enables stable and hardware-friendly INT8 training across a range of network architectures (e.g., ResNet, MobileNetV2, and VGG16) with minimal accuracy degradation.

Ongoing climate change drives drought events that threaten crop yields worldwide. Traditionally, the focus has been on plant breeding to mitigate losses due to stress; however, this approach fails to leverage the resources available within the holobiont. Microbial treatments have been shown to confer drought tolerance by altering phytohormone levels, enhancing nutrient acquisition, and improving water retention in their plant hosts. However, the role of core seed-associated endophytic fungi in stress resilience remains underexplored. Using Moesziomyces antarcticus RS1, which was previously identified as a core fungus in wild and domesticated rice seed microbiomes, we revealed the functional roles of a core microbe in the host plant’s physiology. M. antarcticus RS1 displayed nutrient- and osmotic stress-responsive dimorphism, consistent with adaptive persistence in the seed endosphere. M. antarcticus RS1 inoculation on rice seed significantly improved yield traits by increasing grain quantity and biomass. Notably, M. antarcticus RS1 seed-inoculated rice performed better under PEG-induced osmotic stress, which was associated with increased osmoprotectant levels and growth benefits observed under PEG-treated and untreated conditions. Treatment of M. antarcticus RS1 was associated with increases in drought-related class 2 and class 3 Late Embryogenesis Abundant gene expression in rice, including a suite of RAB dehydrins. These findings establish M. antarcticus RS1 as a core seed endophyte that improves rice drought tolerance and productivity, positioning it as a novel bioinoculant for sustainable agriculture, particularly in water-limited environments.

Recent mixture of experts (MoE)-based transformer models have achieved remarkable performance across various applications. However, as model size increases, the associated memory demand escalates dramatically, limiting their deployment in resource-constrained edge environments. To address this challenge, this study investigates the trade-off between performance and computational overhead under extreme compression conditions by applying ternary quantization and additional compression schemes to MoE models. Experimental results demonstrate that Huffman coding achieves a higher compression ratio but suffers from substantial decoding latency, while dictionary coding provides a lower compression ratio with significantly faster decoding. These findings highlight that efficient deployment of MoE models requires an integrated compression framework that jointly optimizes compression ratio and overhead. Furthermore, based on these observations, potential research directions are suggested, including hybrid coding formats and look-up table-based dedicated hardware accelerators for efficient MoE model compression.

BACKGROUND:Harnessing beneficial soil microbes provides an eco-friendly alternative to pesticides for sustainable crop protection. Members of the genus Streptomyces combine broad antagonistic activity with plant immune priming and growth promotion, yet their ecological roles and field reliability remain insufficiently understood. We investigated the soil actinobacterium Streptomyces murinus JS029 in the Brassica rapa-Sclerotinia minor pathosystem to elucidate its mechanisms of pathogen suppression, plant immune activation and rhizosphere microbiome modulation, and to develop a field-deployable formulation. RESULTS:Streptomyces murinus JS029 secreted chitinase, cellulase and protease and produced the polyene macrolides pentamycin and filipin I, which are known to disrupt fungal cell walls and plasma membranes. Plants exposed to Streptomyces murinus JS029 exhibited strong activation of salicylic acid, jasmonic acid and ethylene signalling pathways and were associated with enhanced biomass and strong protection against Sclerotinia minor. A barley-based solid formulation ensured reproducible field efficacy, reducing disease by approximately 70-80%. Rhizosphere sequencing revealed increased fungal richness and distinct bacterial-fungal compositional shifts, indicating functional reassembly of the soil microbiome. Genome analysis and ultraviolet (UV) mutagenesis linked antifungal activity to a polyene biosynthetic gene cluster. CONCLUSION:Streptomyces murinus JS029 integrates direct antagonism, immune priming and microbiome restructuring to support disease-suppressive soils. These findings provide mechanistic insights and a practical framework for deploying multifunctional Streptomyces bioinoculants as sustainable alternatives to chemical fungicides in integrated pest management systems. © 2026 Society of Chemical Industry.

Recently, vision–language models (VLMs) have delivered state-of-the-art multi-modal accuracy, yet deploying them on FPGA/ASIC accelerators remains costly: after quantizing general matrix multiply (GEMM) to low-bit integer math, non-linear functions (NLFs) dominate resources and power. Prior NLF approximations either adopt high-precision piecewise-linear (PWL) methods that still consume substantial logic/DSP budgets, or low-precision integer surrogates that necessitate fine-tuning to recover accuracy. In this paper, we present hardware-efficient, training-free approximations for two representative NLFs, namely GELU and LayerNorm. First, for GELU, we propose a power-of-two (PoT) PWL scheme: we analytically study the LUT-entry/accuracy trade-off under input clipping, introduce an automatic clipping-point selection to meet a target error, and convert segment slopes to PoT to replace multipliers with shifts. Second, for LayerNorm, we eliminate floating-point operations in quantized pipelines via a PoT-based mean estimator and a log-based shift-LUT approximation of the reciprocal square root for variance normalization. Both designs compile a common shift-add datapath and co-optimize naturally with quantized GEMM. On quantized CLIP-ViTs, our approach is plug-and-play (no additional training) and incurs at most a 0.93% Top-1 drop on ImageNet. A prototype on Xilinx FPGA reduces DSP usage by up to 100%, LUTs by 69.8%, and FFs by 96.0%, delivering substantial gains in resource efficiency and deployability. These results indicate that simple, PoT-driven approximations can cap NLF overheads and enable practical, resource-aware VLM acceleration on reconfigurable and custom silicon. We provide the HI-APP implementation at https://github.com/IDSL-SeoulTech/HI-APP.

With the emergence of transformer-based models that have demonstrated remarkable performance in natural language processing tasks, large language models (LLMs) built upon the transformer architecture and trained on massive datasets have achieved outstanding results in various tasks such as translation and summarization. Among these, decoder-only LLMs have garnered significant attention due to their superior few-shot and zero-shot capabilities compared to other architectures. Motivated by their exceptional performance, numerous efforts have been made to deploy decoder-only LLMs on diverse hardware platforms. However, the substantial computational and memory demands during both training and inference pose considerable challenges for resource-constrained hardware. Although efficient architectural designs have been proposed to address these issues, LLM inference continues to require excessive computational and memory resources. Consequently, extensive research has been conducted to compress model components and enhance inference efficiency across different hardware platforms. To further accelerate the inherently repetitive computations of LLMs, a variety of approaches have been introduced, integrating operator-level optimizations within Transformer blocks and system-level optimizations at the granularity of repeated Transformer block execution. This paper surveys recent research on decoder-only LLM inference acceleration, categorizing existing approaches based on optimization levels specific to each hardware platform. Building on this classification, we provide a comprehensive analysis of prior decoder-only LLM acceleration techniques from multiple perspectives.

Vision Transformers (ViTs) deliver superior accuracy but incur prohibitive computational costs for on-device inference due to multiplication-intensive matrix operations. We present SHARP, a fine-tuning-free ViT accelerator that combines sensitivity-aware mixed quantization with a fully pipelined architecture. SHARP assigns one of three quantization schemes—INT, Power-of-Two, or Hybrid—to each static matrix multiplication based on layer-wise sensitivity analysis, replacing a substantial fraction of multiplications with hardware (HW)-efficient shift operations while preserving model accuracy. To effectively support this mixed quantization approach, SHARP introduces dedicated compute engines optimized for each quantization scheme and employs resource allocation-based pipeline balancing to eliminate bubbles and maximize throughput. Implemented on a Xilinx ZCU102 FPGA, SHARP achieves 69.34% Top-1 accuracy on DeiT-Tiny without fine-tuning and delivers 351.2 FPS at 31.38 FPS/W. Compared to CPU, SHARP demonstrates 26.8× and 26.3× improvements in FPS/W and GOPS/W, respectively.

Proteins destined for secretion typically contain N-terminal signal sequences that target nascent chains to the endoplasmic reticulum. Following targeting, these sequences are cleaved by the heterotetrameric signal peptidase complex (SPC). Despite a conserved N-terminal, hydrophobic core, and C-terminal tripartite organization, their sequences are highly variable. How SPC subunits contribute to recognition of these diverse sequences remains poorly understood. Sec11, the catalytic subunit of the SPC, contains an N-terminal transmembrane domain and a C-terminal hydrophobic region. The latter was unresolved in human SPC cryo-EM structures, likely due to intrinsic flexibility, yet AlphaFold predictions of the yeast SPC suggest that this region forms a C-terminal short helix (CTS) strategically positioned within the presumed signal sequence-binding site. This structural arrangement led us to hypothesize its possible role in substrate handling during signal peptide processing and we undertook to investigate its function using biochemical assays combined with molecular dynamics simulations. Topology mapping confirmed that the Sec11 CTS traverses the endoplasmic reticulum membrane and molecular dynamics simulations showed that removal of the Sec11 CTS does not substantially alter overall SPC architecture or the proximal membrane environment. While N-terminal signal sequences of varying hydrophobicity were efficiently cleaved, internal signal sequences with extended N-terminal region were selectively defective in cleavage in the absence of the Sec11 CTS. These data suggest that the Sec11 CTS specifically stabilizes internal signal sequences for productive engagement with SPC.

The rapid scaling of large language models (LLMs) has made memory capacity, bandwidth, and energy efficiency critical bottlenecks for practical deployment. Quantization is an effective approach for mitigating these costs, but conventional tensor- and channel-level quantization suffers from severe accuracy loss due to outliers in LLM weights and activations. Although block quantization improves robustness by localizing outlier effects, straightforward block-size reduction introduces substantial metadata overhead and significantly increases the hardware cost of post-processing units (PPUs) and accumulators. Furthermore, existing outlier-aware block quantization methods still exhibit limited block-size scalability and depend on simplified online outlier detection criteria that fall short of mean square error (MSE)-based optimality. This paper presents BGM, a GEMM accelerator for LLM inference that co-designs outlier-aware mixed-block-size quantization and dedicated hardware support. The proposed merge-and-split block (M&SB) quantization employs a 1:1:2:4 mixed-block-size structure that selectively splits only outlier-containing sub-blocks while merging the remaining sub-blocks, thereby reducing quantization error and compensating for metadata overhead. To support this mixed-block-size execution efficiently, we design a block processing unit (BPU) with a Sub-PPU and a 2-depth FIFO-based dynamic scheduling mechanism, which avoids the linear hardware overhead growth of naive designs. We further propose zero-counting and variance-based criterion (ZVC), a lightweight online criterion that enables split/merge decisions without the expensive quantization-dequantization-error accumulation required by MSE-based selection. RTL synthesis and accelerator-level evaluations demonstrate that BGM achieves 2.95 & times; higher core energy efficiency than the strongest baseline accelerator, together with up to 3.04 & times; speedup and 2.90 & times; energy reduction in end-to-end simulations. These results establish BGM as an efficient and scalable hardware architecture for practical quantized LLM inference.

On-device transformer inference faces a growing bottleneck in which non-linear functions (e.g., exponential (EXP), reciprocal, reciprocal square root, GeLU, and SiLU) contribute significantly to inference latency as matrix operations become highly optimized. Existing approximation methods either rely on operator-specific datapaths with poor hardware reusability or exhibit a suboptimal accuracy-resource balance with conventional look-up table (LUT)-based piecewise linear approximation (PWL) under stringent edge constraints. This work presents LUT-APP, a unified dynamic-precision LUT-based PWL approximation framework that reconciles accuracy and hardware efficiency across diverse non-linear operators. First, a dynamic fixed-point format (DFF) adaptively allocates bit-width based on input magnitude and parameter scaling to handle the wide dynamic range of EXP. Second, a genetic adaptive differential evolution (GADE) algorithm synthesizes non-uniform PWL segments to minimize approximation error for a given LUT budget. Third, hardware-efficient DFF processing units enable a unified INT8 multiply-add datapath, allowing a single reusable implementation across functions. Experimental results demonstrate that LUT-APP reduces approximation error by up to 6.87× versus state-of-the-art methods while preserving baseline accuracy in large language models and vision transformers without fine-tuning. Hardware synthesis with a 28nm technology shows 4.19× lower area and 3.26× lower power savings than existing LUT-based PWL approaches, validating LUT-APP as a practical, resource-constrained solution for on-device accelerators. We provide the LUT-APP implementation at https://github.com/IDSL-SeoulTech/LUT-APP

Large language models (LLMs) deliver strong natural language processing performance, but ever-growing parameter counts strain memory and power budgets for on-device deployments. Quantization alleviates these costs; however, the outlier-heavy statistics of LLM activations and weights force calibration-based static schemes to retain high-precision fallbacks for dynamically varying values, yielding heterogeneous execution paths and overheads. Microscaling (MX) applies blockwise dynamic quantization with a per-block shared exponent, achieving a homogeneous execution path. Nevertheless, at 4-bit precision, prior work faces three limitations: (i) fixed bins fail to capture block-specific distributions and outliers; (ii) quantization error due to the limited resolution of shared-exponent scaling; and (iii) a lack of co-design approaches that balance model quality and hardware efficiency. We propose BOLD-Q, an HW/SW co-design quantization framework that combines the logarithmic number system (LNS) with MX. BOLD-Q introduces blockwise Dual-Bias—selected statically for weights via candidate search and dynamically computed for activations—to shift and refine per-block quantization bins, while LNS-based scaling improves distributional fit. On LLaMA-2 7B, BOLD-Q limits perplexity increase to +0.32 (W4/A8) and +0.60 (W4/A4), outperforming same-precision baselines. We further design an LNS-MAC systolic array with a lightweight preprocessing row that derives and broadcasts Dual-Bias, eliminating per-PE bias units; within the array, multiplies become log-domain additions, and rescaling is adder-based. Compared with a baseline, BOLD-Q reduces area by up to 34.0% and energy by 21.4%, enabling a homogeneous, on-device-friendly, low-precision execution path for LLMs. The code is available at https://github.com/IDSL-SeoulTech/BOLD-Q.

The impressive success of large language models (LLMs) across a broad spectrum of NLP tasks has attracted considerable attention in both academia and industry. However, their inference incurs substantial computational and memory overhead, making it challenging to efficiently deploy them in latency-sensitive or resource-constrained environments. This survey provides a comprehensive overview of model-level optimization techniques developed to address these issues. Specifically, we examine efficient module designs for core Transformer components-including multi-head attention, feed-forward networks, normalization, and positional encoding-and summarize representative compression methods such as quantization, pruning, knowledge distillation, approximation, and parameter sharing. We categorize recent advances in each area, analyzing their algorithmic principles, empirical trade-offs, and impact on inference efficiency. Furthermore, we propose practical design strategies that effectively combine efficient modules with compression techniques to significantly reduce inference costs while meeting application-specific accuracy and latency requirements.

Rapid advancements in large-scale deep neural networks (DNNs) have increased the demand for substantial data storage and memory bandwidth, resulting in the well-known data movement bottleneck in traditional von Neumann-based architectures. Processing-in-memory (PIM) technology, which integrates computation within memory, has emerged as a promising solution to address this challenge. Previous PIM research utilized in-house PIM simulators to validate this new architecture; however, evaluation performed using in-house PIM simulators suffers from lower versatility and slower evaluation runtimes than emulation. To address these limitations, we present HERMeS , a high-speed, trace-based PIM emulation platform that offers high reliability, fidelity, and versatility. HERMeS separates the PIM controller and PIM emulator regions to achieve a modular design, enhancing versatility, and leverages SystemVerilog to enable high-fidelity implementation on field-programmable gate arrays (FPGAs). To maximize the speedup, we introduce a minimal block RAM (BRAM) unit ( i.e. , pim-tile ) to efficiently manage the limited BRAM resources of the FPGA and optimization techniques to prevent runtime degradation caused by the underutilized pim-tile . We demonstrate the versatility of HERMeS within the class of DRAM-based bank- and bank-group-level digital PIM architectures by implementing representative pre-existing designs in this domain, including AiM and PIM-HBM. Because these target architectures are designed to accelerate DNN inference, the evaluation is conducted primarily on DNN inference workloads, which constitute the natural application domain of this class of PIM designs. Compared to existing in-house PIM simulators, HERMeS demonstrates exceptional accuracy with an average cycle error rate of just 1.57%, while achieving up to 230.24 \(\times\) faster runtime, underscoring its efficacy as a high-performance PIM emulation framework.

Large-scale vision–language models (VLMs) excel at multimodal reasoning, yet efficiency collapses when vision tokens—often orders of magnitude more than text—dominate compute and memory. Prior token-reduction strategies typically trade off salience (which is prone to position bias and incurs extra computation) against diversity (which can under-cover salient regions and is sensitive to hyperparameters). We present SPLIT, a theoretically grounded framework that jointly preserves salience and diversity while aggressively eliminating redundancy. SPLIT (i) estimates token importance via temporal shifts of hidden states across layers—eschewing attention scores and their biases; (ii) assigns adaptive region-level budgets to guarantee localized coverage; and (iii) selects tokens using a diversity score that prioritizes distinctive, non-redundant representations. Our analysis shows that adaptive budgeting yields tighter coverage guarantees than uniform allocation, and our selection rule maintains diversity without costly tuning. Empirically, SPLIT consistently outperforms state-of-the-art on image and video understanding benchmarks. On image understanding with LLaVA-1.5-7B, SPLIT preserves over 99\% accuracy with 192 vision tokens and about 92.8\% with only 64 tokens, demonstrating robust performance under severe token budgets. These results indicate that SPLIT delivers scalable, attention-score-free token reduction that makes multimodal reasoning substantially more efficient without sacrificing accuracy.

On-device AI has received increasing attention due to its ability to provide personalized performance, reduce server load, and address privacy concerns. In this context, efforts have been made to deploy deep learning models on power-efficient hardware platforms, such as field-programmable gate arrays (FPGAs). Specifically, various pruning techniques have been devised to improve performance and energy consumption. However, prior pruning methods fail to achieve balanced hardware utilization, which limits actual performance gains. This paper proposes SPEED, a hardware-aware structured pruning framework integrated into FPGA-based convolutional neural network (CNN) accelerators. SPEED introduces a novel processing unit (PU)-aware kernel block pruning technique for balanced computation across a PU array. Additionally, it proposes an adaptive kernel merging technique to minimize information loss during pruning. Experiments on ResNet18, ResNet50, and YOLACT using ImageNet and Pascal VOC2012 datasets show that SPEED achieves comparable accuracy to software-based pruning methods while achieving higher throughput and lower latency, validated on two types of processing elements. Specifically, for ResNet18, SPEED removes 57.9% of parameters and 44.6% of FLOPs with only a 0.91% drop in Top-1 accuracy, and for ResNet50, it removes 73.2% of parameters and 66.0% of FLOPs with a 1.20% drop in Top-1 accuracy. FPGA benchmarking results show that SPEED efficiently converts reductions in floating-point operations into actual speedups, with little increase in hardware resource usage. When deployed on an FPGA board, SPEED improves FPS by 42.2% and enhances power efficiency by 42.7% compared to the baseline. Case studies in CNN classification and instance segmentation models demonstrate the effectiveness of SPEED as a practical pruning solution for FPGA-based CNN accelerators.