Nonlinear activation plays an essential role in neural networks (NNs) for their generalization ability. However, implementing intricate mathematical operations on hardware platforms, including field-programmable gate arrays (FPGAs), presents significant challenges. Prior works based on piecewise functions or look-up table (LUT) have encountered difficulties in balancing precision requirements with fair hardware overhead and often necessitating complex manual interventions. To address these issues, this article proposes DIF-LUT Pro, an automated tool for simple yet scalable approximation for various nonlinear activations on FPGA. Specifically, the proposed algorithm achieves self-adaptive hardware design oriented toward target precision, by piecewise linear matching to fit the function derivative roughly and range addressable LUT to offset the difference. Moreover, DIF-LUT Pro integrates the algorithm into an automated tool, allowing users to configure the customized interface and generate the corresponding hardware description language (HDL) code with a single click. Experimental results show that 1) DIF-LUT Pro features robust automation and fair generality, capable of generating equitable hardware designs under various user configurations across different FPGA platforms and 2) DIF-LUT Pro produces approximations that are simple yet effective, achieving competitive performance compared to previous expert-crafted designs. Furthermore, two detailed case studies demonstrate the efficient application of DIF-LUT Pro on NeRF and SEResnet, proving its practical value. Our source code is open-source and available at https://github.com/AdrianLiu00/DIF-LUT-Tool.

Advances in Large Language Models (LLMs) have paved the way for Multimodal Large Language Models (MLLMs). Among these, Large Audio Language Models (LALMs) are essential for realizing universal auditory intelligence. Despite their remarkable performance, the escalation of LALMs' capabilities has significantly outpaced the development of systemic frameworks to ensure their trustworthiness. This survey provides a comprehensive investigation into the endogenous mechanisms of LALMs, detailing the architectural innovations and alignment algorithms that facilitate emergent reasoning. Specifically, we analyze how the transition to unified end-to-end frameworks and the integration of continuous acoustic signals expand the attack surface. To rigorously evaluate the risks within these paradigms, we establish a comprehensive taxonomy of trustworthiness, categorizing critical vulnerabilities such as cross-modal jailbreaking, latent acoustic backdoors, and biometric privacy leakage. We review the state-of-the-art LALMs through six analytical pillars: hallucination, robustness, safety, privacy, fairness, and authentication. The pronounced imbalance between a mature offensive landscape and underdeveloped defenses highlights persistent trustworthiness gaps and multidimensional risks in audio-centric intelligence. Finally, we propose a roadmap advocating for “Defense-in-Depth” architectures, causal auditory world modeling, and intrinsic representation engineering to support the development of more reliable and trustworthy audio intelligence. Our project has been uploaded to GitHub https://github.com/Kwwwww74/Awesome-Trustworthy-AudioLLMs.

The Segment Anything Model with Concepts (SAM3) heralds a new paradigm for open-vocabulary segmentation through natural language interaction, offering significant potential for medical image analysis. However, effectively adapting such a powerful vision-language model to the diverse and nuanced domain of medical imaging remains a key challenge. Naive fine-tuning is parameter-inefficient, while standard Mixture-of-Experts (MoE) methods introduce prohibitive computational overhead, limiting their clinical applicability. To address this, we propose Dual-Adaptive SAM3 (DA-SAM3), a novel framework that achieves both high segmentation accuracy and extreme parameter efficiency via a dual-adaptive specialization mechanism. Our first adaptation is task-aware: a Dynamic Expert Router (DER) that sparsely activates the most relevant experts by jointly reasoning about the visual input and the textual concept prompt, mimicking a clinical consultation process. Our second adaptation is parameter-aware: a Decomposed Parameterized Experts (DPE) design that represents each expert as a shared frozen base (inherited from the pretrained SAM3) and a lightweight trainable low-rank delta, reducing MoE parameter overhead by over 80%. Extensive experiments on multiple public medical segmentation benchmarks demonstrate that Dual-Adaptive SAM3 not only matches or exceeds the accuracy of fully fine-tuned SAM3 and standard MoE baselines, but also achieves a notable 5% gain over current state-of-the-art methods, with interpretable results validating its effectiveness. The code is available at: https://github.com/Reconsider80/DA-SAM3.

Large Language Model-based Multi-Agent Systems (LLM-MASs) have demonstrated remarkable real-world capabilities, effectively collaborating to complete complex tasks. While these systems are designed with safety mechanisms, such as rejecting harmful instructions through alignment, their security remains largely unexplored. This gap leaves LLM-MASs vulnerable to targeted disruptions. In this paper, we introduce Contagious Recursive Blocking Attacks (Corba), a novel and simple yet highly effective attack that disrupts interactions between agents within an LLM-MAS. Corba leverages two key properties: its contagious nature allows it to propagate across arbitrary network topologies, while its recursive property enables sustained depletion of computational resources. Notably, these blocking attacks often involve seemingly benign instructions, making them particularly challenging to mitigate using conventional alignment methods. We evaluate Corba on two widely-used LLM-MASs, namely, AutoGen and Camel across various topologies and commercial models. Additionally, we conduct more extensive experiments in open-ended interactive LLM-MASs, demonstrating the effectiveness of Corba in complex topology structures and open-source models. Our code is available at: https://github.com/zhrli324/Corba.

Vision Transformers (ViTs) have achieved high performance across various computer vision tasks by leveraging the attention mechanism. However, the attention module in ViTs severely hindered inference performance due to its low operational intensity. Existing approaches improve ViTs efficiency through pruning, sparsity, and linearization, but at the cost of fine-tuning overhead and accuracy degradation. In this paper, we propose PipeViT, a memory-efficient and low-latency accelerator for ViTs inference. The key insight of PipeViT is to exploit intra-layer acceleration opportunities. Specifically, we first fuse the attention operations into a single operator to reduce memory access overhead. Then, we divide the input of attention into multiple tiles to reduce the on-chip memory requirement. Finally, we pipeline the tiled attention computation to improve overall throughput. Based on the optimized dataflow, we design a heterogeneous dual-core architecture for efficient pipeline execution. Furthermore, to maximize hardware utilization, the architecture can be reconfigured into a single core with higher parallelism during the execution of the feed-forward network. Experimental results show that PipeViT achieves up to $19.3 \times 1.5 \times, 2.1 \times$, and $2.0 \times$ improvements in Frames Per Second (FPS) compared to state-of-the-art accelerators, including ViTA, Auto-ViT, MEViT, and HeatViT. Additionally, PipeViT achieves up to $8.0 \times$ and $2.6 \times$ higher energy efficiency compared to CPU and GPU implementations, respectively.

Detailed routing constitutes a critical phase in the very large-scale integration (VLSI) physical design, widely regarded as the most time-consuming and computationally intensive step in the back-end design process. Due to its iterative nature and strong data dependencies, conventional parallel acceleration techniques often suffer from limited scalability and effectiveness. To address these challenges, we propose RouterAcc, an FPGA-based software–hardware co-design acceleration framework tailored for VLSI detailed routing. RouterAcc incorporates an access analysis mechanism and a termination condition strategy to accelerate convergence. Furthermore, we employ a hierarchical storage mapping scheme and a flexible dimension-partitioning architecture to alleviate memory bottlenecks and enhance data locality. Additionally, RouterAcc leverages a hierarchical comparison pipeline with fully parallelized computing units and a data preprocessing strategy to maximize computational efficiency. Experimental results on the ISPD’18 benchmarks demonstrate that RouterAcc achieves consistent speedups of 2.1×–2.3× over TritonRoute with less than 1% quality degradation. With further co-optimization, RouterAcc attains speedups of 2.7×–11.8× while maintaining routing quality comparable to TritonRoute and surpassing Dr.CU 2.0 as well as the state-of-the-art (SOTA) FPGA-based approaches.

Resource Consumption Attacks (RCAs) have emerged as a significant threat to the deployment of Large Language Models (LLMs). With the integration of vision modalities, additional attack vectors exacerbate the risk of RCAs in large vision-language models (LVLMs). However, existing red-teaming studies have mainly overlooked visual inputs as a potential attack surface, resulting in insufficient mitigation strategies against RCAs in LVLMs. To address this gap, we propose RECITE (Resource Consumption Red-Teaming for LVLMs), the first approach for exploiting visual modalities to trigger unbounded RCAs red-teaming. First, we present Vision Guided Optimization, a fine-grained pixel-level optimization to obtain Output Recall Objective adversarial perturbations, which can induce repeating output. Then, we inject the perturbations into visual inputs, triggering unbounded generations to achieve the goal of RCAs. Empirical results demonstrate that RECITE increases service response latency by over 26 ↑, resulting in an additional 20% increase in GPU utilization and memory consumption. Our study reveals security vulnerabilities in LVLMs and establishes a red-teaming framework that can facilitate the development of future defenses against RCAs.

As LLM-based agents become increasingly prevalent, triggers implanted in user queries or environment feedback can activate hidden backdoors, raising critical concerns about safety vulnerabilities in agents.However, traditional backdoor attacks are often detectable by safety audits that analyze the reasoning process of agents, hindering further progress in agent safety research.To this end, we propose a novel backdoor implantation strategy called Dynamically Encrypted Multi-Backdoor Implantation Attack . Specifically, we introduce dynamic encryption, which maps the backdoor into benign content, effectively circumventing safety audits.To enhance stealthiness, we further decompose the backdoor into multiple sub-backdoor fragments. Based on these advancements, backdoors are allowed to bypass safety audits significantly.Additionally, we present AgentBackdoorEval , a dataset designed for the comprehensive evaluation of agent backdoor attacks.Experimental results across multiple datasets demonstrate that our method achieves an attack success rate approaching 100% while maintaining a detection rate of 0%, illustrating its effectiveness in evading safety audits.Our findings highlight the limitations of existing safety mechanisms in detecting advanced attacks, underscoring the urgent need for more robust defenses against backdoor threats.Code and data are available at https://github.com/whfeLingYu/DemonAgent.

In recent years, although wireless rechargeable sensor networks have broken through the energy bottleneck of traditional sensor networks, the wireless charging process has the risk of sensor location privacy leakage, and the attacker can extrapolate the distance by observing the behavior of the mobile charger (MC), leading to a privacy leakage rate as high as 52%, threatening the network topology integrity and data security. In this article, we construct a hybrid location privacy attack framework, reveal the attack principle, and build the framework based on least squares and center of mass method, and verify its efficiency. After introducing the evaluation method, simulations and experiments show that the model doubles the localization accuracy, but the number of location privacy leaking nodes increases by 33.3%.

Binarization is a promising approach to significantly reduce computational complexity by replacing multiplications with hardware-efficient XNOR operations. However, the binarization of LLM activations often leads to severe accuracy degradation, while weight-only binarization fails to eliminate multipliers due to the Self-Attention mechanism. Furthermore, LLMs exhibit distinctive channel-level data distribution characteristics and differing computational and memory requirements between the Pre-fill and Decoding stages, necessitating a specialized inference framework. In response, we introduce XShift, an algorithm-hardware co-design framework optimized for efficient binarized LLM inference on FPGAs. XShift incorporates three key contributions: (1) a hardware-friendly XNOR-Shift Encoding (XSE) format that transforms traditional multiplications into XNOR and shift operations, ensuring scalability and precision; (2) Hardware Adaptive Outlier and Sparsity (HAOS) techniques, which exploit channel-level data distribution and systolic array architectures for optimized quantization and sparsification; and (3) a dedicated hardware accelerator featuring an XNOR-Shift Systolic Array (XSSA) and an enhanced Base-2 SoftMax Converter (BSMC), designed to address the specific computational demands of binarized LLMs. Experimental evaluations on the Alveo U280 and U50 FPGA demonstrate that XShift achieves a 10-15x reduction in DSP resource usage while surpassing existing accelerators and GPUs in inference performance. Specifically, XShift delivers an average speedup of 4.17-4.76x and a 14.29-6.95x improvement in energy efficiency, alongside lower perplexity compared to other low-precision LLM techniques. These results underscore the potential of XShift for edge deployment of LLMs.

This paper introduces FAMERS, a tile-based hardware accelerator designed for efficient 3D Gaussian Splatting (3DGS) inference on edge-deployed Field Programmable Gate Arrays (FPGAs). 3DGS has emerged as a powerful technique for photorealistic image rendering, leveraging anisotropic Gaussians to balance computational efficiency and visual fidelity. However, the high memory and processing demands of 3DGS pose significant challenges for real-time applications on resource-constrained edge devices. To address these limitations, we present a novel architecture that optimizes both computational and memory overheads through model pruning and compression techniques, enabling high-quality rendering within the constrained memory and processing capabilities of edge platforms. Experimental results demonstrate that our implementation on the Xilinx XC7K325T FPGA achieves a 1.99x speedup and 13.46x energy efficiency compared to NVIDIA RTX 3060M Laptop GPU, underscoring the viability of our approach for real-time applications in virtual and augmented reality.

Applications constructed with multiple Deep Neural Networks (multi-DNNs) are growing rapidly in edge and data center. However, executing multi-DNNs efficiently remains chal-lenging because multi-DNNs are inherently heterogeneous. The diverse operators, dependencies and performance requirements of multi-DNNs lead to high costs of encoding and generalization. We introduce Taichi, a graph-based framework for efficiently scheduling multi-DNNs on multi-core accelerators. Specifically, Taichi consists of two phases: (1) a graph neural network (GNN) is utilized to automatically capture the features from the graph structure of multi-DNNs and (2) reinforcement learning (RL) is employed to find an optimal online scheduling strategy. Evaluation results show that TaiChi reduces latency by 1.1-2.4 x and 1.1-1.6x compared to SJF and MAGMA, and improves throughput by 26.4-63.7% and 18.6-33.7%, respectively. Moreover, TaiChi achieves an average speedup of 779 x in scheduling runtime compared to MAGMA.

The row-wise product algorithm shows significant potential for sparse matrix-matrix multiplication (SpGEMM) on hardware accelerators. Recent studies have made notable progress in accelerating SpGEMM using this algorithm. However, several challenges remain in accelerating imbalanced SpGEMM, where the distribution of non-zero elements across different rows is imbalanced. These challenges include: (1) the fixed dataflow of the merger tree, which leads to lower PE utilization, and (2) highly imbalanced data distributions, such as single rows with numerous non-zero elements, which result in intensive computations. This imbalance significantly challenges SpGEMM acceleration, leading to time-consuming processes that dominate overall computation time. In this paper, we propose AiSpGEMM to accelerate imbalanced SpGEMM on FPGAs. First, we improved the (CSR)-S-2 format to adapt it for imbalanced SpGEMM acceleration based on the row-wise product algorithm. This reduces off-chip memory bank conflicts and increases data reuse of matrix B. Secondly, we design a reconfigurable merger (R-merger) with flexible interconnects to improve PE utilization. Additionally, we propose an intra-row parallel merging algorithm and its corresponding hardware architecture, the parallel merger (P-merger), to accelerate intensive operations. Experimental results demonstrate that AiSpGEMM achieves a geometric mean (geomean) speedup of 5.8x compared to the state-of-the-art FPGA-based SpGEMM accelerator. In Geomean, AiSpGEMM achieves a 3.0x speedup and a 9.8x improvement in energy efficiency compared to the NVIDIA cuSPARSE library running on an NVIDIA A6000 GPU. Moreover, AiSpGEMM-21 demonstrated a 4x increase in average throughput compared to the same GPU.

In the back-end verification of integrated circuits (IC), design rule checking (DRC) plays a critical role in ensuring that the layout complies with process constraints and guarantees manufacturability. Traditional DRC for 2D layouts involves checks on parameters including line width, spacing, and density. With the advancement of 3D IC and advanced packaging technologies, new DRC requirements have emerged. These include checks on inter-die spacing, alignment relationships, and the handling of non-Manhattan geometries. Previous academic research has focused almost exclusively on optimizing 2D DRC. Meanwhile, industrial tools such as Calibre 3DSTACK can only perform 3D rule checks on layouts that have already passed 2D DRC, which increases both workflow complexity and time consumption. Targeted at these limitations, we propose 3D DRC, a U-Net-based DRC tool designed for 3D IC. Our method performs both 2D and 3D rule checks in a single pass on 3D structures, with specific optimizations for non-Manhattan geometries in 3D IC. Additionally, the tool also supports traditional 2D DRC when applied to purely 2D layouts. We evaluated the performance of 3D DRC on a variety of open-source PDK rule sets. Extensive experiments demonstrate that the model exhibits strong generalization and high accuracy, achieving an average recall of 97.5% and precision of 97.7%. Furthermore, the model demonstrates high runtime efficiency, with the 2D mode running 22.3× faster than Calibre nmDRC, and the 3D mode being 13.3× faster than Calibre 3DSTACK.

Hyperdimensional computing (HDC) has emerged as a promising cognitive computing paradigm, offering exceptional robustness and energy efficiency for intelligent applications. However, the computational demands of HDC, particularly during the encoding and associative search phases, pose significant challenges due to their time and resource intensity. In this paper, we propose LUT-HD, a software-hardware co-design framework that accelerates HDC inference by leveraging efficient table lookup techniques. First, we introduce a binary code quantization (BCQ) algorithm based on a lookup table (LUT) that transforms costly matrix-vector multiplications in HDC into simple table lookups using precomputed results. Next, we propose a custom FPGA-based accelerator tailored for LUT-based HDC to strike a balance between accuracy and efficiency. This accelerator incorporates a performance-optimized pipeline for encoding and associative search, enhancing computational speed and resource utilization. Experimental results demonstrate that LUT-HD achieves up to 14.6 × inference speedup and reduces 97.3% energy consumption compared to the GPU platform. In addition, compared to state-of-the-art (SOTA) HDC solutions, LUT-HD offers a 5.5× speedup with negligible accuracy loss and reduces 44.8% energy consumption.

Electromigration-related reliability concerns in very large-scale integration (VLSI) circuits have garnered increasing attention as technology continues to scale. As integrated circuits shrink and their density rises, solving Korhonen's equation for the multi-segment interconnect line model becomes increasingly challenging. Recent advances in neural network-based approaches have demonstrated notable efficacy in addressing differential equations arising in physical modeling frameworks. Inspired by Physics-Informed Graph Neural Network (PIGNN) methodologies, we propose a novel Physics-Informed Message Passing (PIMNEM) architecture designed to solve coupled multi-domain Korhonen equations. At the same time, we introduce AdaptEM, which incorporates a graph partitioning mechanism with a hierarchical training strategy and employs the PIM-NEM architecture as a subgraph computation unit. AdaptEM enables multi-scale decomposition of interconnected circuits and facilitates hierarchical unsupervised learning via its hierarchical architecture. Unsupervised training is first applied to partitioned subgraphs using the PIMP mechanism, followed by global graph fine-tuning, where inter-subgraph boundary constraints are explicitly enforced through differentiable penalty terms. AdaptEM achieves a 20× speedup over FEM-based methods at the cost of about 0.5% accuracy loss. While AdaptEM may not match the absolute computational speed of state-of-the-art EM tools, its end-to-end unsupervised training framework, enhanced by a hierarchical subgraph training strategy, offers superior generalization capabilities and greater tuning flexibility.

Aiming at the problems of low coverage, poor connectivity, and high energy consumption in 3-D heterogeneous wireless sensor networks (3-D HWSNs), this article constructs a multiobjective coverage optimization model that balances coverage, connectivity, and energy consumption. Meanwhile, this article proposes a multiobjective spider wasp optimizer (MOSWO) based on a spider wasp optimizer (SWO) to solve the problem. First, incorporating an external archive allows MOSWO to obtain and store Pareto optimal solutions. Second, an important-objective trend operator and improving SWO's mating behavior enhance the algorithm's optimization ability. Finally, A spherical divergence operator is introduced to reduce the redundancy of sensor nodes. To compare the coverage optimization performance of the proposed algorithm, MOSWO MOAAO, MOEA/D, MOPSO, MOAHA, and NSGA-II are used to solve the MCO problem of 3-D HWSNs in obstacle and no-obstacle scenes. The experimental results show that the Pareto front of MOSWO is optimal compared to the Pareto fronts of MOAAO, MOEA/D, MOPSO, MOAHA, and NSGA-II. MOSWO performs effectively in improving coverage and network connectivity, reducing energy consumption.