Processing-in-Memory (PIM) promises to reduce data movement overhead by executing computation in or near memory, but its realized application speedup remains highly design-dependent. Non-offloadable host execution, host-PIM transfers, limited PIM capacity, and device programming latency can limit end-to-end speedup, making fast early-stage design-space exploration (DSE) essential. However, existing PIM evaluation methods remain limited: circuit- and device-level tools cannot capture these end-to-end PIM performance factors, while cycle-accurate simulation is too slow for iterative DSE. To address this gap, we present VIPER, a unified, lightweight, and architecture-aware performance evaluation framework for PIM DSE. VIPER profiles host execution once and combines the measured host behavior with a PIM-aware analytical engine that sweeps PIM-side parameters across candidate designs. It supports both Processing Near Memory (PNM) and Processing Using Memory (PUM) under task-offloading and data-triggered execution by capturing host-PIM transfer, array access, in-memory computation, device programming latency, and capacity-induced partitioning, providing rapid architecture-aware performance estimates for iterative DSE without repeated cycle-accurate simulation. We validate VIPER against a commercial UPMEM system and more than 400 cycle-accurate gem5 configurations. VIPER predicts the UPMEM offloading decision and break-even region a priori, and, with a refined transfer model, captures the measured peak-and-rolloff behavior with 12% mean speedup error across the DPU sweep (6% up to the 256-DPU peak). Against gem5, VIPER achieves less than 10% error while reducing evaluation time from hours to under one minute. Case studies of UPMEM, ReRAM/FeFET crossbars, and IMCRYPTO show that architecture-aware DSE reveals key performance trade-offs that device-level evaluation misses.

Content-addressable memory (CAM), through supporting massively parallel search, holds great promise for many data-intensive applications, such as information retrieval, anomaly detection, and genomics. Motivated by multi-level cell (MLC) capabilities of emerging memory devices, recent advances in circuit and architecture design of CAM have explored analog CAMs (ACAMs) and multi-bit CAMs (MCAMs), opening new frontiers for improving storage density and energy efficiency, as well as enabling emerging applications. A significant challenge in designing ACAM/MCAM lies in managing inherent device and circuit non-idealities, which can inadvertently degrade application-level accuracy. This paper presents several representative ACAM and MCAM circuit and architecture designs based on different emerging memory devices, including resistive RAM, ferroelectric FETs, and Flash memory. Innovative device- and circuit-level techniques for mitigating the negative impact of these non-idealities are discussed. Furthermore, hardware-algorithm codesign approaches for enhancing overall system robustness are illustrated through accelerating two representative applications. Finally, a general CAM evaluation framework will be discussed with special emphasis on predicting the impact of the device and circuit non-idealities on application-level accuracy.

Ventricular arrhythmias (VAs), particularly ventricular tachycardia and fibrillation, remain a leading cause of sudden cardiac death. Implantable cardioverter defibrillators (ICDs) can deliver life-saving shocks, but inappropriate shocks degrade patient outcomes and device efficiency. While deep learning has improved VA detection accuracy, it lacks uncertainty quantification (UQ), limiting clinical acceptability. This article introduces a Bayesian convolutional neural network (Bayes-CNN) accelerator, designed for real-time intracardiac electrogram classification within ICDs. It combines a fully digital 1-D convolution pipeline for feature extraction with a mixed-signal, compute-in-memory (CIM) Bayesian classifier. By embedding a 360-fJ/Sample Gaussian random number generator within the CIM tile, this 0.816-mm(2) design delivers 350-pW VA detection with UQ, enabling a selective prediction strategy that reduces inappropriate shocks without compromising reliability.

Aerial search and rescue missions require fast and reliable victim detection under uncertain and rapidly changing environments. Deterministic deep learning models can produce overconfident false positives, forcing unmanned aircraft systems to perform costly verification maneuvers that reduce search coverage and increase rescue delay. Bayesian neural networks provide uncertainty-aware detection, but their sampling overhead is challenging for battery-constrained edge platforms. This work presents a FeFET-based Bayesian inference engine with a write-free central limit theorem Gaussian random number generator embedded in a compute-in-memory macro. By summing currents from a randomly selected subset of minimum-sized, programmed-once FeFETs, the proposed architecture eliminates energy- and endurance-intensive write operations during inference while maintaining scalable Gaussian sampling. The CLT-GRNG consumes 640 aJ per sample, providing a 560x energy-efficiency improvement over prior BNN accelerators, while the CIM tile achieves 185 TOPS/W/mm2. Evaluated on aerial search and rescue detection, the Bayesian model improves uncertainty calibration and robustness under environmental corruption, reducing risk and enabling low-confidence detections to be filtered before costly verification. These results demonstrate an energy-efficient and uncertainty-aware edge AI engine for autonomous search and rescue systems.

Earth Mover's Distance (EMD) is an important similarity measure between two distributions, used in computer vision and many other application domains. However, its exact calculation is computationally and memory intensive, which hinders its scalability and applicability for large-scale problems. Various approximate EMD algorithms have been proposed to reduce computational costs, but they suffer lower accuracy and may require additional memory usage or manual parameter tuning. In this paper, we present a novel approach, NNS-EMD, to approximate EMD using Nearest Neighbor Search (NNS), in order to achieve high accuracy, low time complexity, and high memory efficiency. The NNS operation reduces the number of data points compared in each NNS iteration and offers opportunities for parallel processing. We further accelerate NNS-EMD via vectorization on GPU, which is especially beneficial for large datasets. We compare NNS-EMD with both the exact EMD and state-of-the-art approximate EMD algorithms on image classification and retrieval tasks. We also apply NNS-EMD to calculate transport mapping and realize color transfer between images. NNS-EMD can be 44x to 135x faster than the exact EMD implementation, and achieves superior accuracy, speedup, and memory efficiency over existing approximate EMD methods.

Privacy has rapidly become a major concern/design consideration. Homomorphic encryption (HE) and garbled circuits (GC) are privacy-preserving techniques that support computations on encrypted data. HE and GC can complement each other, as HE is more efficient for linear operations, while GC is more effective for non-linear operations. Together, they enable complex computing tasks, such as machine learning, to be performed exactly on ciphertexts. However, HE and GC introduce two major bottlenecks: an elevated computational overhead and high data transfer costs. This paper presents Privacy Preserving In-Memory Computing Engine (PPIMCE), an in-memory computing (IMC) fabric designed to mitigate both computational overhead and data transfer issues. Through the use of multiple IMC cores for high parallelism, and by leveraging in-SRAM IMC for data management, PPIMCE offers a compact, energy-efficient solution for accelerating HE and GC. PPIMCE achieves a 107x speedup against a CPU implementation of GC. Additionally, PPIMCE achieves a 1 500x and 800x speedup compared with CPU and GPU implementations of CKKS-based HE multiplications. For privacy-preserving machine learning inference, PPIMCE attains a 1 000x speedup compared with CPU and a 12x speedup against CraterLake, the state-of-art privacy preserving computation accelerator.

We present a hybrid, general-purpose, associative processing-in-memory architecture that combines the energy and area advantages of a primary FeFET-based CAM array with the write performance and endurance of a much smaller CMOS-based sidekick. The hybrid nature of the architecture is transparent to the programmer, who uses a RISC-V ISA with standard RVV vector extensions. Detailed SPICE- and system-level simulations show our hybrid design dramatically curbs the endurance disadvantages of a pure FeFET design and delivers, on average, 30% and 11% area and energy savings over a purely CMOS implementation, respectively, at a performance loss of barely 1% over pure CMOS.

Homomorphic encryption (HE) provides strong security and privacy guarantees for the cloud-edge computinga paradigm by enabling computation directly on encrypted data. However, large ciphertexts and complex operations incur high computational costs. Crossbar array (XBA)-based Computing-in-Memory (CiM) hardware has the potential to significantly enhance the performance of HE, while reducing energy consumption and chip area, owing to high memory density and computational parallelism. Moreover, intrinsic non-idealities in XBAs, including programming and cycle-to-cycle variations, could actually be exploited to implement certain functionalities required by HE algorithms. However, XBA-induced noise can exceed the error tolerance of HE algorithms. To evaluate the feasibility of employing XBAs for HE acceleration, two critical questions must be answered: (1) Can the noise introduced by XBAs be leveraged as part of the HE encryption process? and (2) How much noise can be tolerated by an HE algorithems, without compromising the computational correctness? This work answers these questions through both theoretical analysis and experimental study for the CKKS-based encryption. We introduce EvaX-poly, a general noise evaluation framework for XBA designers to quantify the impact of XBA noise on HE computation and determine whether a given XBA device can support a target HE workload. Using EvaX-poly, one can systematically evaluate the signal-to-noise ratio (SNR) for both the HE algorithm and the XBAs, thereby determining whether the noise level of a specific XBA implementation is acceptable for HE acceleration. Moreover, leveraging experimentally measured device data, we show that the specific XBA hardware can not only support CKKS encryption but also outperforms a state-of-the-art ASIC HE accelerator, achieving 4.5× higher throughput per-area energy product.

Data transfer between processors and memory remains a critical bottleneck in improving application performance on traditional computing hardware, particularly for data-intensive workloads such as machine learning, bioinformatics, and security applications. In-memory computing (IMC), a paradigm where a substantial portion of data processing occurs directly within memory, has emerged as a promising solution to mitigate this bottleneck. The advancement of emerging non-volatile memory (NVM) technologies has further accelerated the development of IMC hardware fabrics. However, harnessing the full potential of IMC requires a cross-layer design approach that spans memory technologies, circuits, architectures, and systems. Essential cross-layer tools—including modeling and simulation, data partitioning and mapping, and operation scheduling—play a pivotal role in designing efficient IMC-based hardware. This article reviews key advancements in simulation and design tools for IMC fabrics, with a focus on NVM-based crossbar arrays and content-addressable memories, while highlighting the necessity of cross-layer collaboration. Additionally, we discuss current challenges and emerging opportunities in the field.

Content-Addressable Memories (CAMs) enable data retrieval based on content rather than specific addresses, making them invaluable for rapid data search and pattern matching. Efficient computation in these systems requires minimal latency and power consumption, particularly for embedded applications. The parallelization of in-memory computing (IMC) significantly enhances both search latency and power efficiency. This work presents, the use of ferroelectric field-effect transistors (FeFETs) in a 1 kb CAM array, applied to two key use cases: one/few-shot learning in memory-augmented neural networks and read mapping in genome analysis for bioinformatics. Both applications demonstrate software-level accuracy alongside ultra-low power consumption.

This paper presents a novel content-addressable memory (CAM) array fabricated in a 28 nm ferroelectric field-effect transistor (FeFET) technology, tailored for rapid exact and approximate associative search. Leveraging a 2FeFET CAM bitcell structure, the design enables low-voltage, energy-efficient computation of Hamming distances directly within memory. The architecture achieves robust variability management through programmable series resistance at the segment level, enhancing sensing accuracy and reliability. Comprehensive device-level characterization validates the feasibility of FeFET-based associative storage, demonstrating stable threshold voltage distributions, low programming variability, high read endurance and retention exceeding 105 seconds. Functionality is further verified through two representative applications: genome read mapping, highlighting efficient parallel k-mer matching, and few-shot learning classification, demonstrating competitive inference accuracy compared to software baselines. Experimental results confirm significant reductions in energy consumption and latency relative to conventional CMOS-based CAM solutions, positioning FeFET CAM arrays as promising candidates for emerging bioinformatics and edge-AI workloads.

Processing-in-memory (PIM) enhances memory with computational capabilities, potentially solving energy and latency issues associated with data transfer between memory and processors. However, managing concurrent computation and data flow within the PIM architecture incurs significant latency and energy penalty for applications. This article introduces Shared-PIM, an architecture for in-dynamic random-access memory (DRAM) PIM that strategically allocates rows in memory banks, bolstered by memory peripherals, for concurrent processing and data movement. Shared-PIM enables simultaneous computation and data transfer within a memory bank. When compared to LISA, a state-of-the-art (SOTA) architecture that facilitates data transfers for in-DRAM PIM, Shared-PIM reduces data movement latency and energy by 5x and 1.2x , respectively. Furthermore, when integrated to a SOTA in-DRAM PIM architecture (pLUTo), Shared-PIM achieves 1.4x faster addition and multiplication, and thereby improves the performance of matrix multiplication (MM) tasks by 40%, polynomial multiplication (PMM) by 44%, and numeric number transfer (NTT) tasks by 31%. Moreover, for graph processing tasks like breadth-first search (BFS) and depth-first search (DFS), Shared-PIM achieves a 29% improvement in speed, all with an area overhead of just 7.16% compared to the baseline pLUTo.

Secure memory systems employing AES-CTR encryption face significant performance challenges due to high counter (CTR) cache miss rates, especially in applications with irregular memory access patterns. These high miss rates increase memory traffic and latency, as each CTR cache miss triggers additional DRAM accesses. To address these bottlenecks and adapt to diverse access patterns, we propose COSMOS (Counter Optimized Secure Memory Operation Scheme), a novel solution leveraging reinforcement learning to reduce long memory access latency. COSMOS integrates two RL-based specialized predictors: one for data location prediction and another for CTR locality prediction, each with a well-defined state space, action space, and reward function. The RL-based data location predictor determines whether data reside on-chip or off-chip after an L1 cache miss, enabling early CTR access for off-chip predictions with minimal changes to the existing cache hierarchy. The RL-based CTR locality predictor identifies CTRs with high locality, supporting a locality-centric CTR cache (LCR-CTR) to improve cache efficiency and reduce miss rates. COSMOS improves performance over MorphCtr by 25% in for irregular memory access applications, with minimal hardware overhead.

Uncertainty estimation is an indispensable capability for AI-enabled, safety-critical applications, e.g. autonomous vehicles or medical diagnosis. Bayesian neural networks (BNNs) use Bayesian statistics to provide both classification predictions and uncertainty estimation, but they suffer from high computational overhead associated with random number generation and repeated sample iterations. Furthermore, BNNs are not immediately amenable to acceleration through compute-in-memory architectures due to the frequent memory writes necessary after each RNG operation. To address these challenges, we present an ASIC that integrates 360 fJ/Sample Gaussian RNG directly into the SRAM memory words. This integration reduces RNG overhead and enables fully-parallel compute-in-memory operations for BNNs. The prototype chip achieves 5.12 GSa/s RNG throughput and 102 GOp/s neural network throughput while occupying 0.45 mm2, bringing AI uncertainty estimation to edge computation.

Integrating deep learning with environmental perception enhances robotic adaptability to complex tasks. However, its "black-box" nature, such as the lack of uncertainty quantification, poses challenges for safety-critical applications, particularly in unstructured and noisy environments. Bayesian neural networks (BNNs) offer uncertainty quantification but are limited by high hardware overhead, restricting real-time implementation on resource-constrained robots. This paper presents a mixed-signal hardware accelerator for BNNs, utilizing probabilistic quantum tunneling in fully depleted silicon-on-insulator (FD-SOI) transistors to enable efficient, real-time uncertainty quantification. Device measurements indicate high-quality Gaussian random variable generation, validated through quantile-quantile plot analysis, with a high correlation coefficient (r = 0.997) at 200 fJ/sample. Leveraging such compact randomness, the parallel architecture achieved 10(3)-10(4)x latency reduction at less than 2x area cost. Finally, in uncertainty-aware visual localization application of autonomous underwater vehicles, the BNN model effectively distinguishes data noise from model uncertainty, yielding significant information gain and enhancing the resampling efficiency by 4.5x at same accuracy.

Multiple research vectors represent possible paths to improved energy and performance metrics at the application-level. There are active efforts with respect to emerging logic devices, new memory technologies, novel interconnects, and heterogeneous integration architectures. Of great interest is quantifying the potential impact of a given solution to prioritize research vectors accordingly. In this paper, we discuss two efforts - one focused on emerging memory technology, and another focused on heterogeneous integration technology - that speak to best practices for, and needed contributions from the design automation (DA) community to explore this vast design space. Furthermore, we highlight new research efforts that aim to develop the novel compiler abstractions and frameworks that are ultimately needed to derive maximum value from new memory and/or heterogeneous and monolithic integration architecture, and that can also play an important role with respect to design space exploration efforts.

Fully Homomorphic Encryption (FHE) allows outsourced computation on clients’ encrypted data while preserving data privacy. FHE’s high computational intensity incurs high overhead from data transfer with hardware such as CPU, GPU, and FPGA, due to the inherent separation between computing and data. To overcome this limitation, Compute-Enabled RAM (CE-RAM) has been explored; however, prior work using CE-RAM to accelerate FHE only explores a simple implementation of a finite-field FHE scheme and did not explore algorithmic optimizations. In this paper, we investigate CE-RAM acceleration FHE more deeply, implementing both the finite-field B/FV and torus-based TFHE cryptosystems in CE-RAM with common FHE optimizations. This is the first work to explore using CE-RAM to accelerate TFHE. For B/FV, we explore parameter-specific algorithmic optimizations specifically designed for CE-RAM friendliness. We evaluate our implementation as compared to prior work in CE-RAM FHE acceleration and other hardware acceleration strategies. We demonstrate speedups of up to 784x for B/FV homomorphic multiplication and 38x for TFHE bootstrapping as compared to CPU implementations. We also discuss the overhead of CE-RAM for FHE on energy and area consumption, showing comparable or improved performance as compared to other work or hypothetical near-memory accelerators.

This article presents a comprehensive physics-based model for back-end-of-line (BEOL)-compa-tible oxide-semiconductor-based ferroelectric field-effect transistors (FeFETs). The proposed model describes the polarization switching behavior and enables bidirectional bias sweeps for the hysteretic IDVG curve. The model has been validated against a TCAD model as well as experimental results. Simulations using the proposed model show that polarization switching during the erase operation is primarily influenced by the fringing field in the absence of holes in the amorphous channel. Furthermore, the memory window (MW) increases as the channel length decreases, which is attributed to the enhanced influence of the fringing field in shorter channel devices, resulting in a larger portion of negative polarization being switched during the erase operation. Simulations using this model suggest an MW of 1.2 V, which shows excellent agreement with experimental data.

As the reliance on secure memory environments permeates across applications, memory encryption is used to ensure memory security. However, most effective encryption schemes, such as the widely used AES-CTR, inherently introduce extra overheads, including those associated with counter storage and version number integrity checks. Moreover, encryption only protects data content, and it does not fully address the memory access pattern leakage. While Oblivious RAM (ORAM) aims to obscure these patterns, its high performance costs hinder practical applications. We introduce Secure Scattered Memory (SSM), an efficient scheme provides a comprehensive security solution that preserves the confidentiality of data content without traditional encryption, protects access patterns, and enables efficient integrity verification. Moving away from traditional encryption-centric methods, SSM offers a fresh approach to protecting data content while eliminating counter-induced overheads. Moreover, SSM is designed to inherently obscure memory access patterns, thereby significantly enhancing the confidentiality of memory data. In addition, SSM incorporates lightweight, thus integrated mechanisms for integrity assurance, protecting against data tampering. We also introduce SSM+, an extension that adapts Path ORAM to offer even greater security guarantees for both data content and memory access patterns, demonstrating its flexibility and efficiency. Experimental results show that SSM incurs only a 10% performance overhead compared to non-protected memory and offers a 15% improvement over AES-CTR mode memory protection. Notably, SSM+ provides an 20% improvement against Path ORAM integrated with Intel SGX under the highest security guarantees.

Deep random forest (DRF), which combines deep learning and random forest, exhibits comparable accuracy, interpretability, low memory and computational overhead to deep neural networks (DNNs) in edge intelligence tasks. However, efficient DRF accelerator is lagging behind its DNN counterparts. The key to DRF acceleration lies in realizing the branch-split operation at decision nodes. In this work, we propose implementing DRF through associative searches realized with ferroelectric analog content addressable memory (ACAM). Utilizing only two ferroelectric field effect transistors (FeFETs), the ultra-compact ACAM cell performs energy-efficient branch-split operations by storing decision boundaries as analog polarization states in FeFETs. The DRF accelerator architecture and its model mapping to ACAM arrays are presented. The functionality, characteristics, and scalability of the FeFET ACAM DRF and its robustness against FeFET device non-idealities are validated in experiments and simulations. Evaluations show that the FeFET ACAM DRF accelerator achieves ∼10 6 ×/10× and ∼10 6 ×/2.5× improvements in energy and latency, respectively, compared to other DRF hardware implementations on state-of-the-art CPU/ReRAM.