The group delay of a signal prior to data monitoring is a crucial consideration in today’s real-time applications, especially for those that involve long sensor arrays or high-order filters. In this article, nine new second-order Negative Group Delay (NGD) circuits based on Current Feedback Operation Amplifier (CFOA) are proposed, and their transfer functions are demonstrated. These circuits have a wide range of applications, from audio to mechanical signals and sensor signal anticipation. An example design procedure is provided for one of the introduced circuits. A time-domain analysis is performed using both a single-tone sinusoidal and a band-limited audio recording in the frequency range of 1 Hz to 500 Hz. The article assesses the change in the signal using Root Mean Square Error (RMSE) and cross-correlation. Furthermore, the relationship between the NGD value and the operation range of the circuit is investigated and verified experimentally. The results show that an NGD value of approximately 100μs can be achieved with an amplitude error of 0.86% for a single-tone input and 1.54% for an audio recording, and an operation range of about 650 Hz.

This paper proposes an operational transconductance amplifier-capacitor-based (OTA-C) negative group delay (NGD) circuit for transimpedance-mode systems. The application areas extend from audio to sensor signal anticipation. Post-layout simulated NGD value of about 200 mu s to 100 ns is observed to be achievable with three different capacitor values without any resistive passive components. The operation range varies from 700 Hz to 700 kHz. The NGD and the operation range are shown to be flexible without gain dependency. An example design is built for a specific NGD value of 15 mu s and time-domain analysis is done with both a single-tone sinusoidal and a band-limited audio record in the range of 1 Hz-7 kHz. The calculated Root Mean Square Error for audio input to the system is only 4.70%.

In this paper, seven different MOSFET-C transimpedance filters with their corresponding transfer functions and basic filter specifications, are provided. Presented designs show second-order standard band-pass, low-pass, or high-pass characteristics. Moreover, some filters provide both low-pass and band-pass characteristics. Especially, having a tunability feature makes a design more useful and applicable for various communication and instrumentation systems. The selected filter topology was biased under various biasing conditions to tune central frequency by keeping bandwidth constant. To elaborate the design with different aspects, we checked its small-signal performance by introducing both changing temperature and implementation errors. The theoretical results are in detail verified by numerous simulations using Cadence IC6 Spectre analog design environment. In the design, transistors with 1.8 V supply voltage were used and modelled by the SilTerra Malaysia 180 nm CMOS process parameters. The implemented layout, including metal-insulator-metal on-chip capacitors, occupies an area of 175 mu m x 75 mu m, while the total power consumption of the filter is found to be only 128.86 mu W.

In this study, MOS-Only transimpedance mode filters are proposed. The presented circuits use two capacitors and MOS transistors that operate in saturation mode. The circuits are additional examples contributing to the set of previously published circuit topologies. One of the circuits is chosen and its functionality is verified with simulations. An important aspect of the chosen design is the versatility of filter parameters. Changing the drain currents of MOSFETs makes it possible to adjust the center frequency after production. We performed simulations with the LTSPICE simulation program using 0.18 μm TSMC CMOS technology. Simulation results are found in close agreement with the theoretical results.

In this paper, a lattice network-based second-order all-pass filter (APF) design is presented. Unlike previously published works, floating active inductors (FAIs) are used in the lattice topology. Inductance (L) and quality factor (Q) tunability of Q-enhanced FAIs are employed to ensure the designed APF is robust to process-voltage-temperature (PVT) variations and to make the filter's group delay responses are constant for a wide frequency range. The operation of the proposed APF is verified by post-layout simulations using Cadence Design Suite in TSMC 65-nm CMOS technology. The operating frequency of the designed filter reaches 5 GHz with a delay range of 24.5-50 ps. The designed filter has a gain of -0.15 dB, which varies up to 1.47 dB in the operating frequency range. The group delay error is 114 fs, which is a 0.294% variation in the nominal case. The input-referred 1 dB compression point (P1dB) and the third-order interception point (IIP3) values are attained as -5.21 dBm and +9.19 dBm, respectively. At the nominal condition, the noise figure is achieved as 16.7 dB. The circuit occupies only 0.0189 μm2 while drawing 29 mA from a 1.5 V supply.

In this paper, a dual output current-mode biquad filter with band-pass and low-pass outputs using MOS transistors and capacitors is presented. In these type of filters MOSFETs operating in saturation mode are used instead of standard active elements and transconductances of these transistors are utilized instead of resistors. In the study a voltage controlled current source (VCCS) based core filter circuit is presented. This circuit is used as a starting point for the complete filter design. After VCCSs are replaced by MOSFETs biased for operating in saturation region, a resistorless MOSFET-C type filter circuit is obtained with only seven transistors and two grounded capacitors. Also, an agile filter application for secure communication is given to illustrate the functionality.

This paper presents the design of a wide-tunable, low-voltage, small-area LC voltage-controlled oscillator (LCVCO). Instead of a spiral inductor, a novel active inductor is used in the conventional bottom-biased NMOS cross-coupled LC-VCO architecture. The oscillator, designed in TSMC 65 nm CMOS process and post-layout simulated in Cadence Design Suite, operates at a frequency range of 2.4 to 3.8 GHz and draws 8.5 mA from a 1.2 V supply. At a 1 MHz offset, the circuit has a phase noise of -80.22 dBc/Hz. The designed circuit has a differential output swing of 56.1 mV, and the percentage of total harmonic distortion (%THD) is determined as 3.47% in the nominal case. The designed LC-VCO consumes only 0.013 mm2 silicon area. Additionally, a buffer circuit is presented that can be utilized to make the oscillation rail-to-rail.

In this paper, we present six area-efficient transimpedance type second-order analog filters. There are many applications where the available signal is current, however the necessary signal for further processing is voltage type. For such applications the presented circuits will be a useful solution. The technique employed is called MOS-only technique and to the best of our knowledge this is the first attempt to implement transimpedance type filters with MOS-only technique. Starting from the core circuit biasing is illustrated and the functionality is shown with LT SPICE simulations using TSMC 0.18u technology parameters. From six core circuits one circuit is selected and the design is completed for illustration purpose.

In this study, a MOS-Only Band-Pass transimpedance-mode filter is proposed. The presented circuit uses two capacitors and three MOS transistors that operate in saturation mode as active elements. One important aspect of the design is versatility of filter parameters. By changing drain currents, it is possible to adjust center frequency and quality factor after production. Circuits are biased with a single 1.8V power supply. We performed simulations with LTSPICE simulation program using $0.18\mu \mathrm{m}$ TSMC CMOS technology. Simulation results are found in close agreement with theoretical results.

Background:Electrical impedance spectroscopy (EIS) is a fast, non-invasive, and safe approach for electrical impedance measurement of biomedical tissues. Applied to dental research, EIS has been used to detect tooth cracks and caries with higher accuracy than visual or radiographic methods. Recent studies have reported age-related differences in human dental tissue impedance and utilized fractional-order equivalent circuit model parameters to represent these measurements. Objective: We aimed to highlight that fractional-order equivalent circuit models with different topologies (but same number of components) can equally well model the electrical impedance of dental tissues. Additionally, this work presents an equivalent circuit network that can be realized using Electronic Industries Alliance (EIA) standard compliant RC component values to emulate the electrical impedance characteristics of dental tissues. Results: To validate the results, the goodness of fits of electrical impedance models were evaluated visually and statistically in terms of relative error, mean absolute error (MAE), root mean squared error (RMSE), coefficient of determination (R2), Nash–Sutcliffe’s efficiency (NSE), Willmott’s index of agreement (WIA), or Legates’s coefficient of efficiency (LCE). The fit accuracy of proposed recurrent electrical impedance models for data representative of different age groups teeth dentin supports that both models can represent the same impedance data near perfectly. Significance: With the continued exploration of fractional-order equivalent circuit models to represent biological tissue data, it is important to investigate which models and model parameters are most closely associated with clinically relevant markers and physiological structures of the tissues/materials being measured and not just “fit” with experimental data. This exploration highlights that two different fractional-order models can fit experimental dental tissue data equally well, which should be considered during studies aimed at investigating different topologies to represent biological tissue impedance and their interpretation.

Electrical impedance spectroscopy (EIS) is a fast, non-invasive, and safe technique for bioimpedance measurement. In dental research, EIS has been used to detect tooth cracks and caries with higher accuracy than visual and radiographic methods. Recently, a study has been reported on effect of age on impedance measurements for two age groups by employing EIS. The aim of that study was to demonstrate the usefulness of fractional calculus in equivalent circuit modeling. In proposed double dispersion Cole impedance (C-C) models, both resistance and pseudo-capacitance values were found to be significantly different for both age groups. However, in our study, the first time it was found out that proposed models' total pseudo-capacitance values of both young and old dentines can be reduced by 34% and 7.5%, respectively, if recurrent electrical impedance model for n = 2 bifurcations to be used. Secondly, new empirical fractional-order electrical models of human tooth using the optimized Valsa network with EIA standard compliant RC values are reported that provide better understanding of the structure of dentine from resistance and capacitance point of view.

The design trend in the analog CMOS signal processing technology is towards the MOS-only approach. Using this technique, this work presents three new core topologies realizing floating positive or negative inductance simulators. The positive inductance simulator (PIS) is investigated as both integer- and fractional-order element. For illustration purpose, the behavior of the fractional-order PIS was tested via implementation in RLC ladder prototype of voltage-mode (VM) high-pass filter with various orders; particularly of orders 2, 2.5, and 3. The performance of the integer-order PIS was tested in third-order VM elliptic low-pass filter at very high frequencies. Theoretical results are verified by LTSPICE simulations using BSIM3 1 μm technology transistor parameters.

MOS-only type signal processing devices received significant attention mainly due to trends in analog design works toward low-voltage low-power designs. Using this approach many limitations of analog filters especially frequency limitation among others is less pronounced compared to classical approach employing Op-Amps, Operational Transconductance Amplifiers, Current Conveyors, or similar active elements. In this work we present three MOS-only type current-mode analog functional filter cores. For illustration purpose, an application filter design example is given that is a novel filter topology and compared with its counterparts previously published in the literature.

In this paper, an area efficient CMOS first-order voltage-mode (VM) all-pass filter (APF) is proposed. The introduced resistorless MOS-only core circuit consists of three transistors only. For the design three transconductances and one gate-to-source capacitance of MOS transistors are sufficient instead of external passive resistors and capacitors, while the full implementation of the VM APF consists of 12 MOS transistors and one grounded capacitor only. Hence, the proposed circuit exhibits important features such as simplicity, permitting reduced chip area when integrated and wide operating frequency range compared to classical analog counterparts that require active elements employing large number of transistors. The theoretical results are in detail verified by numerous post-layout simulations using Cadence IC6 Spectre analog design environment. In the design, medium V-th transistors with 1.8 V supply voltage were used and modeled by the TSMC 180 nm CMOS process parameters available in EUROPRACTICE IC Service design kit. The post-layout simulated pole frequency of the VM APF is 4.825 MHz, the implemented layout including metal-insulator-metal on-chip capacitor occupies an area of 31.1 mu m x 39.5 mu m, while the total power consumption of the filter is found to be only 92.57 mu W. (C) 2019 Elsevier GmbH. All rights reserved.

In this paper, we present two area-efficient transimpedance type second-order analog filters. In many applications the signal generated and available is current, however the necessary signal for further processing is voltage type. For these applications the presented circuits will be very useful. The technique employed is MOS-only technique and to the best of our knowledge this is the first attempt to implement transimpedance filters with MOS-only technique. Starting from the core circuit biasing is illustrated and the functionality is shown with LTSPICE simulations using TSMC 180nm technology parameters.

The aim of this paper is to present a work towards a MOS transistor memristor emulator. The starting circuit employs an opamp, negative capacitors and loaded with a nonlinear resistor. The final aim is to design a memristor with only MOS transistors which is easily integrable. To implement the negative capacitance several possible potential circuit examples of MOS-Only type are given. These capacitors realize floating negative capacitances and the ac small signal form is shown. Some simulation results are included to verify theory.

In this paper, a set of current-mode MOSFET-C multifunction filters are presented. Since MOS transistors operating in saturation region are used instead of the passive resistors, key filter parameters are all electronically controllable. The main properties of a total of eight different multifunction filters are catalogued in tabular form. The proposed circuits exhibit attractive features such as circuit simplicity and reduced chip area compared to the classical analog filters that require active elements including large number of transistors. All the filters are simulated in spectre simulation software in Cadence design environment using 90 nm UMC CMOS process parameters.

Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C 0.96 with 12 pF · sec -0.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range 1 MHz-1 GHz it shows only ±0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from -1.85% to +0.73%. SPICE simulations are given to prove the theory.

Recently, many active filter circuits that use only MOS transistors were presented in the literature. In these circuits, instead of passive resistors, transconductances of MOSFETs operating in saturation region are used. Moreover, their parasitic gate to source capacitances are employed instead of passive capacitors. These circuits provide circuit implementation with fewer transistors and eliminate the need for external passive elements. In this study, a MOS-only third order Butterworth filter for high frequency applications has been proposed. The circuit leads to a compact circuit having fewer number of transistors compared to classical active block-based analog counterparts. Simulation results agree well with the theoretical study.