Noisy industrial environments are challenging for effective communication. To facilitate communication between workers in noisy environments, active systems featuring interpersonal radio communication may be used despite the fact that these systems do not enable users to dynamically address specific individuals or perceive the directionality in speech. A promising approach to these challenges is an emerging technology called radio acoustical virtual environment (RAVE). RAVE aims to improve communication in two ways: (1) allowing users to dynamically address specific individuals based on vocal effort, and (2) transforming speech signals to convey spatial directionality of its origin. To explore its potential, a mockup version of RAVE incorporating key algorithms was developed and evaluated with 18 participants. The evaluation demonstrated RAVE's potential to improve communication. Additionally, the results offer valuable insights into user interaction and inform future design decisions for active hearing protection devices with integrated communication systems.

In this paper, a low-complexity approach for the automorphism ensemble decoder (AED) using successive cancellation (SC) as constituent decoders is proposed. The approach sequentially activates sub-decoders and terminates the decoding process based on pre-optimized parameters, derived from the strong correlation observed between the decoding outcome and the SC path metric. An algorithm is proposed to find a list of early termination thresholds that minimize average decoding complexity subject to a block-error rate (BLER) constraint. For various code parameters and a BLER below 10^-3, simulation results show that average decoding complexity is reduced by a factor of at least 6 ×, and up to 22 ×, compared to the original AED complexity, with a negligible degradation in BLER.

Cryptographic wallets play a vital role in securing digital assets within blockchain networks by managing private keys that authorize secure transactions. However, side channel analysis (SCA) attacks have become a serious threat, enabling attackers to extract sensitive information by exploiting algorithmic weaknesses in microcontroller-based wallets, resulting in the loss of millions of dollars in digital assets. In hierarchically deterministic (HD) systems, the compromise of a single primary key can endanger all subsequent child keys, while the use of independent keys for each account introduces complexity and challenges in key management. This work presents HardVault, a field programmable gate array (FPGA)-based cryptocurrency wallet that supports both Bitcoin and Ethereum. HardVault introduces the first hardware wallet architecture that implements both non-deterministic (ND) and HD key generation modes directly in hardware, giving users the flexibility to choose either approach based on their security and usability needs. By leveraging constant-time operations and hardware-enforced private-key isolation, the design significantly improves resilience to SCA attacks. In addition, the architecture prioritizes resource efficiency to minimize area usage without compromising security, making it well-suited for compact, portable hardware wallet applications. Implementation on a ZCU104 FPGA shows that HardVault uses only 27% of available look-up tables (LUTs). Compared to the Trezor One cryptocurrency (crypto) wallet, the proposed implementation achieves $9 imes $ higher energy efficiency, $8 imes $ lower latency, and $7 imes $ higher throughput.

Accurate direction-of-arrival (DOA) estimation is valuable for spatially selective communication in noisy industrial environments. This work investigates a lightweight single-antenna framework in which receiver motion forms a virtual aperture. The receiver uses onboard inertial measurement unit (IMU) headings and two-way-ranging (TWR) measurements to a known fixed beacon, avoiding GPS, optical tracking, and high-precision external tracking of the mobile receiver. The curvilinear virtual-array MUSIC formulation is evaluated numerically using phase-coherent narrowband snapshots over arbitrary trajectories. Hardware experiments validate a range- domain TWR-IMU bearing estimator using corrected and averaged ranging observations. In a campaign of 100 consecutive four-revolution sweeps, all trials are retained. Phase-aligned accumulation recovers a 123 mm range-modulation amplitude, in close agreement with the measured 120 mm antenna lever arm. The single-sweep bearing precision is 8.2° absolute world-frame accuracy is limited by systematic BNO055 magnetometer drift in the motorized setup. The embedded bearing-estimation computation consumes 144.9 mJ per estimate, approximately 3

Polar codes concatenated with a cyclic redundancy check (CRC) code have been selected in the 5G standard with the successive-cancellation list (SCL) of list size L = 8 as the baseline algorithm. Despite providing great error-correction performance, a large list size increases the hardware complexity of the SCL decoder. Alternatively, flip decoding algorithms were proposed to improve the error-correction performance with a low-complexity hardware implementation. The combination of list and flip algorithms, the successive-cancellation list flip (SCLF) and dynamic SCLF (DSCLF) algorithms, provides error-correction performance close to SCL-32 with a list size L = 2 and Tmax = 300 maximum additional trials. However, these decoders have a variable execution time, a characteristic that poses a challenge to some practical applications. In this work, we propose a restart mechanism for list–flip algorithms that allows us to skip parts of the decoding computations without affecting the error-correction performance. We show that the restart location cannot realistically be allowed to occur at any location in a codeword as it would lead to an unreasonable memory overhead under DSCLF. Hence, we propose a mechanism where the possible restart locations are limited to a set and propose various construction methods for that set. The construction methods are compared, and the tradeoffs are discussed. For a polar code of length N = 1024 and rate ¼, under DSCLF decoding with a list size L = 2 and a maximum number of trials Tmax = 300, our proposed approach is shown to reduce the average execution time by 41.7% with four restart locations at the cost of approximately 1.5% in memory overhead.

Ethereum leverages smart contracts (SCs) to power decentralized applications (dApps), with execution handled by the Ethereum virtual machine (EVM) within an Ethereum client. Other blockchain platforms, including Avalanche, Polkadot, Aurora, and Cardano, have also adopted the EVM. However, the performance of the EVM is often constrained by the limitations of general-purpose processors, a challenge that has been explored in the literature. This work aims to further address the limitation by proposing EVMx, a dedicated single-core SC execution engine implemented on a field programmable gate array (FPGA). EVMx follows a processor-like architecture inspired by the RISC philosophy. By exploiting the parallelism and high-speed processing capabilities of FPGA hardware, EVMx achieves a 61% to 99% reduction in execution time for commonly used operation codes compared to traditional central processing unit (CPU)-based environments. Furthermore, EVMx executes entire Ethereum blocks with a percentage reduction in execution time between 6% and 56% against comparable FPGA implementations and 98% to 99% compared to CPU-based EVMs in the literature. These results demonstrate the potential of EVMx to significantly accelerate SC execution and enhance the performance of EVM-compatible blockchains.

Polar codes are a class of linear error-correction codes that have received a lot of attention due to their ability to achieve channel capacity in an arbitrary binary discrete memoryless channel (B-DMC) with low-complexity successive-cancellation (SC) decoding. However, practical implementations often require better error-correction performance than what SC decoding provides, particularly at short to moderate code lengths. Successive-cancellation flip (SCF) decoding algorithm was proposed to improve error-correction performance with an aim to detect and correct the first wrongly estimated bit in a codeword before resuming SC decoding. At each additional SC decoding trial, i.e., decoding attempt beyond the initial unsuccessful trial, one bit estimated as the least reliable is flipped. Dynamic SCF (DSCF) is a variation of SCF, where multiple bits may be flipped simultaneously per trial. Despite the improved error-correction performance compared to the SC decoder, SCF-based decoders have variable execution time, which leads to high average execution time and latency. In this work, we propose the generalized restart mechanism (GRM) that allows to skip decoding computations that are identical between the initial trial and any additional trial. Under DSCF decoding with up to 3-bit flips per decoding trial, our proposed GRM is shown to reduce the average execution time by 25% to 60% without any negative effect on error-correction performance. The proposed mechanism is adaptable to state-of-the-art latency-reduction techniques. When applied to Fast-DSCF-3 decoding, the additional reduction brought by the GRM is 15% to 22%. For the DSCF-3 decoder, the proposed mechanism requires approximately 4% additional memory.

Ethereum blockchain uses smart contracts (SCs) to implement decentralized applications (dApps). SCs are executed by the Ethereum virtual machine (EVM) running within an Ethereum client. Moreover, the EVM has been widely adopted by other blockchain platforms, including Solana, Cardano, Avalanche, Polkadot, and more. However, the EVM performance is limited by the constraints of the general-purpose computer it operates on. This work proposes offloading SC execution onto a dedicated hardware-based EVM. Specifically, EVMx is an FPGA-based SC execution engine that benefits from the inherent parallelism and high-speed processing capabilities of a hardware architecture. Synthesis results demonstrate a reduction in execution time of 72% to 99% for commonly used operation codes compared to CPU-based SC execution environments. Moreover, the execution time of Ethereum blocks on EVMx is up to 6x faster compared to analogous works in the literature. These results highlight the potential of the proposed architecture to accelerate SC execution and enhance the performance of EVM-compatible blockchains.

Cryptocurrency blockchain networks safeguard digital assets using cryptographic keys, with wallets playing a critical role in generating, storing, and managing these keys. Wallets, typically categorized as hot and cold, offer varying degrees of security and convenience. However, they are generally software-based applications running on microcontrollers. Consequently, they are vulnerable to malware and side-channel attacks, allowing perpetrators to extract private keys by targeting critical algorithms, such as ECC, which processes private keys to generate public keys and authorize transactions. To address these issues, this work presents EthVault, the first hardware architecture for an Ethereum hierarchically deterministic cold wallet, featuring hardware implementations of key algorithms for secure key generation. Also, an ECC architecture resilient to side-channel and timing attacks is proposed. Moreover, an architecture of the child key derivation function, a fundamental component of cryptocurrency wallets, is proposed. The design minimizes resource usage, meeting market demand for small, portable cryptocurrency wallets. FPGA implementation results validate the feasibility of the proposed approach. The ECC architecture exhibits uniform execution behavior across varying inputs, while the complete design utilizes only 27%, 7%, and 6% of LUTs, registers, and RAM blocks, respectively, on a Xilinx Zynq UltraScale+ FPGA.

In this paper, two decoding algorithms based on Successive-Cancellation (SC) are proposed to improve the error-correction performance of cyclic redundancy check (CRC) -aided polar codes while aiming for a low -complexity implementation. Comparisons with Dynamic SC Flip (DSCF) and SC Perturbation (SCP) are carried out since the proposed DSCF and Perturbation (DSCFP) and Perturbed DSCF (PDSCF) algorithms combine both methods. The analysis includes comparisons with several code lengths N and various number of decoding attempts T-max. For N = 1024 and the coding rate R =1/2, the DSCF and the SCP algorithms with T-max = 17 are bested by approximately 0.1 dB at block -error rate (BLER) of 0.001. At BLER = 10(-6) and for T-max = 64, the gain is of 0.375 dB and > 0.5 dB with respect to DSCF and SCP, respectively. At high signal-to-noise ratio, the average computational complexity of the proposed algorithms is virtually equivalent to that of SC.

The recently proposed SCLF decoding algorithm for polar codes improves the error-correcting performance of state-of-the-art SCL decoding. However, it comes at the cost of a higher complexity. In this paper, partitioned polar codes tailored for the proposed PSCLF decoding algorithm are used to reduce the complexity of SCLF. Indeed, compared to SCLF, PSCLF allows early termination and is able to restart by skipping part of the decoding tree traversed sequentially. In order to maximize the coding gain, design of partitions tailored to PSCLF is proposed. In this extended paper, dynamic flip metric is used, as well as the possibility to flip multiple times during SCL. An analysis on the impact of this strategy on the early-termination or the CRC collisions encountered in PSCLF is carried out. Error-correction performance of multiple code rates and multiple partition strategies are shown. With the baseline algorithm SCL with L =2 , degradation of 0.05 dB is shown with respect to SCL-64, using ω =3 flip per trial with T_max =300 trials. Numerical results show that the proposed PSCLF algorithm has an error-correction performance gain of up to 0.1 dB with respect to SCLF with same decoding parameters. This work is also compared with existing techniques to reduce the complexity of the SCLF decoding algorithm. The proposed algorithm reduces the complexity up to 77 FER=4· 10^-3 and lower.

The SECP256K1 elliptic curve algorithm is fundamental in cryptocurrency wallets for generating secure public keys from private keys, thereby ensuring the protection and ownership of blockchain-based digital assets. However, the literature highlights several successful side-channel attacks on hardware wallets that exploit SECP256K1 to extract private keys. This work proposes a novel hardware architecture for SECP256K1, optimized for side-channel attack resistance and efficient resource utilization. The architecture incorporates complete addition formulas, temporary registers, and parallel processing techniques, making elliptic curve point addition and doubling operations indistinguishable. Implementation results demonstrate an average reduction of 45 efficiency.

Polar codes are a class of error-correcting codes that provably achieve the capacity of practical channels under the low-complexity successive-cancellation flip (SCF) decoding algorithm. However, the SCF decoding algorithm has a variable execution time with a high (worst-case) decoding latency. This characteristic poses a challenge to the design of receivers that have to operate at fixed data rates. In this work, we propose a multi-threshold mechanism that restrains the delay of a SCF decoder depending on the state of the buffer to avoid overflow. We show that the proposed mechanism provides better error-correction performance compared to a straightforward codeword-dropping mechanism at the cost of a small increase in complexity. In the region of interest for wireless communications, the proposed mechanism can prevent buffer overflow while operating with a fixed channel-production rate that is 1.125 times lower than the rate associated to a single decoding trial.

As hearing protection devices (HPDs) also attenuate voice, workers tend to remove them to talk to each other, disabling their protection. Radio-acoustic virtual environment (RAVE) proposes an ideal situation, where workers can communicate in noisy environments while being protected. The voice is recorded with in-ear microphones (IEM), denoised, and transmitted within a certain communication radius determined by the talker's vocal effort. The audio is played at a comfortable level with directionality. Many articles addressed elements necessary for RAVE, such as voice activity detection [N. Lezzoum et al., in IEEE JCE, 2014, pp. 737–744], wearer induce disturbances detection [F. Bonnet et al., in JERGON, 2019, pp. 102862], and communication radius [R. Bouserhal et al., in JSLHR, 2017, pp. 3393–3403]. This pioneering research integrated them and tested a mock-up version of RAVE in live scenarios. In groups of three, twenty-one participants completed manual tasks that required communication. They used RAVE's mock-up and a broadcasting push-to-talk device, with and without noise presence, totaling four scenarios. Participants completed a questionnaire after each scenario, and their speech and motion were recorded. This research contributed with a mock-up version of RAVE with improved signal treatment for real-time purposes. Our results confirm RAVE's added value and illustrates its potential.

Radio-acoustical virtual environment (RAVE) is a new concept where radio signals are received by workers within a specific range based on their vocal effort and background noise level. In this context, we propose an innovative radio-frequency (RF) system for real-time localization and positioning. The key feature of this solution is its ability to simultaneously allocate time slots for communication and additional slots for ranging measurements. This method incorporates the direction-of-arrival (DOA) and orientation of radios within a dynamic mesh network, distinguishing it from other state-of-the-art techniques. The RAVE’s capability for dynamic resource allocation and adaptive communication strategies enhances performance and efficiently utilizes network resources in challenging industrial environments.

In this paper, we propose a low-latency decoding solution of shortened polar codes based on their automorphism groups. The automorphism group of shortened polar codes, designed according to two existing shortening patterns, are shown to be limited but non-empty, making the Automorphism Ensemble (AE) decoding of shortened polar codes possible. Extensive simulation results for shortened polar codes under AE are provided and are compared to the SC-List (SCL) algorithm. The block-error rate of shortened polar codes under AE matches or beats SCL while lowering the decoding latency.

The recently proposed Successive-Cancellation List Flip (SCLF) decoding algorithm for polar codes improves the error-correcting performance of state-of-the-art SC List (SCL) decoding. However, it comes at the cost of a higher complexity. In this paper, we propose the Partitioned SCLF (PSCLF) decoding algorithm, an algorithm that divides a word in partitions and applies SCLF decoding to each partition separately. Compared to SCLF, PSCLF allows early termination but is more susceptible to cyclic-redundancy check (CRC) collisions. In order to maximize the coding gain, a new partition design tailored to PSCLF is proposed as well as the possibility to support different CRC lengths. Numerical results show that the proposed PSCLF algorithm has an error-correction performance gain of up to 0.15 dB with respect to SCLF. Moreover, the proposed CRC structure permits to mitigate the error-correction loss at low frame-error rate (FER) due to CRC collisions, showing a gain of 0.2 dB at a FER of 10-4 with respect to the regular CRC structure. The average execution time of PSCLF is shown to be 1.5 times lower than that of SCLF, and matches the latency of SCL at FER = 4 center dot 10(-3) and lower.

Polar codes are a class of error-correcting codes that provably achieve the capacity of practical channels. The successive-cancellation flip (SCF) decoder is a low-complexity decoder that was proposed to improve the performance of the successive-cancellation (SC) decoder as an alternative to the high-complexity successive-cancellation list (SCL) decoder. The SCF decoder improves the error-correction performance of the SC decoder, but the variable execution time and the high worst-case execution time pose a challenge for the realization of receivers with fixed-time algorithms. The dynamic SCF (DSCF) variation of the SCF decoder further improves the error-correction performance but the challenge of decoding delay remains. In this work, we propose a simplified restart mechanism (SRM) that reduces the execution time of SCF and DSCF decoders through conditional restart of the additional trials from the second half of the codeword. We show that the proposed mechanism is able to improve the execution time characteristics of SCF and DSCF decoders while providing identical error-correction performance. For a DSCF decoder that can flip up to 3 simultaneous bits per decoding trial, the average execution time, the average additional execution time and the execution-time variance are reduced by approximately 31%, 37% and 57%, respectively. For this setup, the mechanism requires approximately 3.9% additional memory.

Unrolling a decoding algorithm allows to achieve extremely high throughput at the cost of increased area. Lookup tables (LUTs) can be used to replace functions otherwise implemented as circuits. In this work, we show the impact of replacing blocks of logic by carefully crafted LUTs in unrolled decoders for polar codes. We show that using LUTs to improve key performance metrics (e.g., area, throughput, latency) may turn out more challenging than expected. We present three variants of LUT-based decoders and describe their inner workings as well as circuits in detail. The LUT-based decoders are compared against a regular unrolled decoder, employing fixed-point representations for numbers, with a comparable error-correction performance. A short systematic polar code is used as an illustration. All resulting unrolled decoders are shown to be capable of an information throughput of little under 10 Gbps in a 28 nm FD-SOI technology clocked in the vicinity of 1.4 GHz to 1.5 GHz. The best variant of our LUT-based decoders is shown to reduce the area requirements by 23% compared to the regular unrolled decoder while retaining a comparable error-correction performance.

Automorphism Ensemble (AE) decoding has recently drawn attention as a possible alternative to list decoding of polar codes. In this letter, we investigate the distribution of Partially-Symmetric Reed-Muller (PS-RM) codes, a family of polar codes yielding good performances under AE decoding. We prove the existence of these codes for almost all code dimensions for code lengths N ≤ 256. Moreover, we analyze the absorption group of this family of codes under SC decoding, proving that valuable permutations in AE decoding always exist. Finally, we experimentally show that PS-RM codes can outperform state-of-the-art polar-code-construction algorithms in terms of error-correction performance for short code lengths, while reducing decoding latency.