Ring learning with errors (RLWE) is largely adopted in Post-Quantum cryptography and Homomorphic encryption schemes. RLWE cryptosystems are defined over polynomial quotient rings, where polynomial additions/subtractions and multiplication are required. In this paper we propose the implementation of a hardware accelerator for polynomial operations required in RLWE cryptosystems. Such hardware accelerator includes a Arithmetic Logic Unit (ALU) able to perform polynomial additions/subtractions and multiplications. The latter adopts Negative Wrapped Convolution (NWC) and Number Theoretic Transform (NTT) techniques. The hardware accelerator has been integrated in a hardware system for accelerating the NewHope-1024 algorithm, and a demo on a Intel DE4 FPGA board has been developed to test the functionality of the system. Synthesis results on different FPGA technologies are proposed too, showing competitive performances respect to the State of Art.

In application-specific SoCs, the irregularity of the topology ends up in a complex and customized implementation of the routing algorithm, usually relying on routing tables implemented with memory structures at source end nodes. As system size increases, the routing tables also increase in size with nonnegligible impact on power, area, and latency overheads. In this paper, we present a routing implementation for application-specific SoCs able to implement in an efficient manner (with no routing tables and using a small logic block in every switch) a deadlock-free routing algorithm in these irregular networks. The mechanism relies on a tool that maps the initial irregular topology of the SoC system into a logical regular structure where the mechanism can be applied. We provide details for both the mapping tool and the proposed routing mechanism. Evaluation results show the effectiveness of the mapping tool as well as the low area and timing requirements of the mechanism. With the mapping tool and the routing mechanism, complex irregular SoC topologies can now be supported without the need for routing tables.

This paper presents the design and the characterization in nanoscale CMOS technology of a Network Interface (NI) for on-chip communication infrastructure with hardware support of advanced networking functionalities: store & forward (S&F) transmission, error management, power management, ordering handling, security, QoS management, programmability, end-to-end protocol interoperability, remapping. The design has been conceived as a scalable architecture: The advanced features can be added on top of a basic NI core implementing data packetization and conversion of protocols, frequency and data size between the connected Intellectual Property (IP) core and the on chip network. The NI can be configured to reach the desired tradeoff between supported services and circuit complexity.

In application-specific SoCs the topology is usually irregular. In this paper we present a mapping tool able to map the initial irregular topology of a SoC system into a logical regular structure (2D-mesh) where a Logic-Based Distributed Routing mechanism (LBDRx) can be applied. The goal is to implement the routing paths without using memory resources. The original topology is not changed. Evaluation results show the effectiveness of the mapping tool.

In application-specific SoCs, the irregularity of the topology ends up in a complex implementation of the routing algorithm, usually relying on routing tables implemented with memory structures. As system size increases, the routing table increases in size with non-negligible impact on power, area and latency overheads. In this paper we present a routing implementation for application-specific SoCs able to implement in an efficient manner (without requiring routing tables and using a small logic block in every switch) a routing algorithm in these irregular networks. The mechanism relies on a tool that maps the initial irregular topology of the SoC system into a logical regular structure where the mechanism can be applied. We provide details on the mapping tool as well the proposed routing mechanism. Evaluation results show the effectiveness of the mapping tool as well as the low area and timing requirements of the mechanism. With the mapping tool and the routing mechanism complex irregular SoC topologies can now be supported without the use of routing tables.

This chapter addresses the problem of functional verification of IP cores to be integrated in complex embedded systems. After analyzing the limits of methods based on HDL testbenches or formal verification, a pseudo-random coverage-driven approach is presented (verification environment design guidelines together with a final coverage report summary) and applied to a novel Router IP core design, a key component of Network-on-Chip communication infrastructure in embedded systems.

MPSoC platforms face an increasing diversity of traffic requirements due to the interaction between cores. This interaction is driven by the applications run by the user, and leads to the coexistence of the best effort traffic and the guaranteed service traffic in the same platform. We propose Extreme End-to-End Protocol (EEEP) as a new end-to-end flow control protocol to access SDRAMs through a multiport memory controller in NoC-based MPSoCs. Our protocol considers the memory access within a system approach. It exploits the occupancy rate of the requests queue in the memory controller within the policy of the traffic injection at the master Network Interfaces (NIs) level. By controlling the best-effort traffic shape, EEEP improves the bandwidth and the latency of the guaranteed service traffic.

Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high performance integrated circuits wires become the performance bottleneck and we are shifting towards communication centric design paradigms. Networks-on-chip and stacked 3D integration are two emerging technologies that alleviate the performance difficulties of on-chip interconnects in nano-scale designs. In this paper we present a design-time configurable error correction scheme integrated at link-level in the 3D Spidergon STNoC onchip communication platform. The proposed scheme detects errors and selectively corrects them on the fly, depending on the critical nature of the transmitted information, making thus the correction software controllable. Moreover, the proposed scheme can correct multiple error patterns by using interleaved single error correction codes, providing an increased level of reliability. The performance of the link and its cost in silicon and vertical wires are evaluated for various configurations.

Connection-then-credits (CTC) is a novel end-to-end flow control protocol to handle message-dependent deadlocks in best-effort networks-on-chip (NoC) for embedded multicore systems-on-chip (SoCs). CTC is based on the classic end-to-end credit-based flow control protocol but differs from it because it uses a network interface microarchitecture where a single credit counter and a single input data queue are shared among all possible communications. This architectural simplification reduces the area occupation of the network interfaces and increases their design reuse; for instance, the same network interface can be used to connect a core independently of the number of incoming and outgoing communications. CTC, however, requires a handshake preamble to initialize the credit counter in the sender network interface based on the buffering capacity of the receiver network interface. While this necessarily introduces a latency overhead in the transfer of a message, simulation-based experimental results show that the penalty in performance is limited when large messages need to be transferred, thus, making CTC a valid solution for particular classes of applications such as video stream processing.