Continuous monitoring of human respiration is essential for health assessment; however, conventional systems are often bulky and highly susceptible to environmental airflow disturbances. Herein, we report a flexible and lightweight wearable respiration sensor that integrates a negative temperature coefficient (NTC) thermistor with a laser-induced graphene (LIG) thermal actuator to establish a localized and stable thermal field, thereby enhancing signal contrast and robustness. The device performance was systematically evaluated under multidirectional environmental airflow. An interference factor was defined to quantitatively assess airflow-induced disturbances, demonstrating stable operation even under challenging conditions. Furthermore, the sensor accurately captures respiratory signals during diverse daily activities and reliably monitors sleep-related breathing patterns, including apnea-like events and snoring. These results highlight the device's high-fidelity detection capability, strong resistance to environmental interference, and broad potential for real-world wearable respiratory health monitoring.

In this brief, we propose an ultra-low-power mel frequency cepstral coefficients (MFCCs)-free keyword switchable KWS system that supports ten sub-classifiers (2 keywords each, 20 keywords in total) through a time-domain transferred training convolutional neural network (TT-CNN). The proposed TT-CNN reduces the model size by sharing the first two convolutional layers with all the keywords with a transferred training approach. Hence, the power budget for memory and computation is largely reduced. The TT-CNN supports flexible keyword demand in different scenes by selecting different kernels in the custom-designed 5T-SRAM. The time-domain feature of the proposed TT-CNN avoids the power-hungry feature extractor (FEx), further reducing the overall power consumption. To benchmark with the state-of-the-art, we demonstrated the proposed system with two cascaded scalable 10-Class KWS chips in 28nm CMOS. Our design achieves a high accuracy of 92.8% on 20 keywords from the Google speech command dataset (GSCD). It also shows that the memory overhead for each keyword can be reduced by 20% with the lowest reported 20-class KWS power consumption of 1.2 mu W.

Resistance-based temperature sensors feature a compact area $(< 5,000\mu \mathrm{m}^{2})$ [1]–[3] with high accuracy and superior resolution FoM $(< 100\text{fJ} \cdot \mathrm{K}^{2})$ [4], [5]. In contrast to the sensing element using active devices (e.g., BJT and MOSFET) that require biasing, the resistor does not pose restrictions on the $V_{\text{DD}}$. Such property facilitates the deployment of resistor-based temperature sensors in the advanced processes with core $V_{\text{DD}} < 1\mathrm{V}$ (e.g., 0.9V in the selected 28nm process) for integrated-temperature-sensing solutions. Yet, due to the transistors' pronounced non-ideal characteristics (gate tunneling, leakage current, short-channel effect, etc.), achieving decent competitive resolution FoM (R-FoM) with a compact area while upholding accuracy remains a significant challenge [6].

This article presents a resonant switched-capacitor (SC) parallel inductor (ReSC-PL) hybrid buck converter with reduced inductor current for high and wide voltage conversion ratio (VCR). The proposed ReSC-PL buck converter lowers down the switching node voltage with V-IN-related flying capacitors and reduces the inductor current I-L with V-OUT-related flying capacitors. Therefore, it can always effectively reduce I-L to a value below 0.5 similar to 0.67 of the output current I-O for high VCRs ranging from 10 to 20. In addition, by utilizing the parasitic inductor, this design effectively reduces the glitches on the output and forms a resonant SC operation to further improve the conversion efficiency. This work, fabricated in 180-nm Bipolar-CMOS-DMOS (BCD), occupies an area of 8.88 mm(2). Measurement results show that the proposed ReSC-PL buck obtains a peak efficiency of 91.8% and a peak current density of 350 A/cm(3) with a power inductor as small as 2.5 x 2 x 1.2 mm(3), with 12-V input and 0.6-V to 1.2-V output, and 5-A maximum output current.

Antibiotic susceptibility testing (AST) plays a critical role in effective clinical treatment. The digital microfluidics platform provides enhanced automation, precision, and conservation of samples compared to conventional AST methods. However, reliance on off-chip preparation and specialized equipment restricts its practical application. This study introduces an advanced system integrating digital microfluidic control, temperature regulation, illumination, and image analysis for rapid AST. The device features an intuitive touchscreen for easy parameter adjustments and a circuit board for precise internal controls, facilitating bacterial sample manipulation, cultivation and detection. Pre-deposited antibiotics on-chip streamline transport and storage. The share-electrode structure on the DMF chip significantly reduces power consumption, and the innovative anti-evaporation design allows for on-chip bacterial growth. This setup can realize accurate determination of the minimum inhibitory concentration in less than 1 h with gray value analysis for bacterial detection. Broad applicability of the system in AST has been validated with various bacteria, either gram positive or gram negative, and different types of antibiotics. Real-time bacterial growth curve analysis completes AST in 4 h, one-fifth the time of standard methods with comparable accuracy. The system was also applied to real sample with mixed species, accomplishing rapid on-site AST without tedious initial bacterial concentration adjustments. The proposed device offers a crucial advantage over existing solutions, enabling timely antibiotic selection in critical situations.

This article for the first time introduces the blue-sideband excitation (BSE) scheme to two types of 2-degree-of-freedom (2-DoF) weakly coupled electrostatic resonant sensors, i.e., a 2-DoF electrostatically coupled resonating system with parallel suspension beams (Device 1) and a 2-DoF coupled double-ended tuning fork (DETF) resonant device (Device 2), boosting the functionality of the mode localization phenomena and ultimately achieving distinct performance upgradation. The amplitude ratio (AR) is hence adopted as the readout metric for the sensitivity characterization with respect to different external stiffness perturbations introduced by the capacitive transduction. Three paradigms of AR were implemented in this subject, namely, intermodal AR (IM-AR), interresonator AR (IR-AR), and interresonator-IM-AR (IRIM-AR), owing to the feature of simultaneous multiple-mode excitation of BSE. A comparison regarding the coupled resonant devices subject to the conventional drive scheme and the BSE was conducted, where the experimental results indicated that more than two orders of magnitude enhancement in sensitivity were achieved with the BSE scheme, along with the possibility of a pronounced $\sim$17 times improvement in the noise floor, as well as the capability of simultaneous multiple parameter extraction across different resonators and vibration modes within the coupled system. This work further verified the feasibility and effectiveness of the BSE scheme, demonstrating the potential of such a technique for sensing applications based on mode-localized resonant sensors, fostering ultrahigh performance augmentation.

Sensor nodes with machine learning (ML) are adept at analyzing intricate environmental and physiological data patterns at the edge [1]–[9]. The design of such ultra-low-power (ULP) devices strives to reduce power consumption, which ensures continuous and energy-harvested operation even with fluctuating ambient available energy levels down to 100nW [10]–[11]. Consequently, ML capabilities on such ULP devices are constrained to perform lightweight detection for events such as voice activity [3] [6], arrhythmia [4] [8], and bearing anomalies [9]. Yet, these isolated, monomodal sensing paradigms suffer from low task complexity and accuracy for overlooking fused information from spatially distributed sensor networks. Additionally, real-world applications subject to data distribution drifts necessitate model adaptability to maintain accuracy in ever-changing environments [12]. Also, current ULP neural network (NN) accelerators consume significant power, limiting their ability to expand the network size, while impeding the overall ML performance.

The floating-point (FP) format offers superior precision compared to its integer counterpart for multiply-and-accumulate (MAC) computations. With the rapid progress of artificial intelligence (AI), FP-MAC operations are increasingly moving from the cloud to edge devices. However, the complex nature of FP processes constrains their energy efficiency. Compute-in-memory (CIM) shows promise for reducing power consumption, but FP-CIM still encounters challenges related to mantissa and exponent computations. This article presents an energy-efficient FP-CIM macro designed for edge-AI devices. It addresses energy efficiency bottlenecks through three key features: 1) an FP digital-to-analog converter (FP-DAC) simplifies the pre-alignment logic, thereby reducing undesired power overhead throughout the FP process; 2) an FP analog-to-digital converter (FP-ADC) that substitutes uniform quantization steps with FP steps, eliminating redundant conversion power through adaptive quantization range (AQR); and 3) a hierarchical-hybrid structure (HHS) optimizes the tradeoff between accuracy and energy efficiency in FP-CIM using a coarse-to-fine hybrid strategy. Fabricated in a 65-nm CMOS process, the prototype FP-CIM macro achieves 54.4 TFLOPS/W in the BF16 mode and 130.9 TFLOPS/W in the FP8 mode.

This article presents a compact wire-metal-based temperature sensor for thermal detection in advanced technologies. The key innovations include: 1) a fractional-discharge scheme originated by extracting the fractional pulse from the five-phase voltage-controlled ring oscillator (VCRO) to shrink the discharge window in the front end (FD) to 10% of a complete clock cycle, preserving the power budget while eliminating the need for bulky metal resistors; and 2) a voltage-to-time (V2T) converter with chopping implemented as an amplifying stage inside the frequency-locked loop (FLL), eliminating the undesired dc offset and 1/f-noise to safeguard the sensing accuracy and resolution. Prototyped in 28-nm CMOS process, this sensor occupies a footprint of 4100 mu m(2) and consumes 10.5 mu W under 0.8-V VDD at room temperature. It demonstrates outstanding 3 sigma inaccuracies of +/- 1.5 degrees C/ +/- 0.2 degrees C after one-/two-point trimmings across -40 degrees C to 125 degrees C. The resolution figure of merit (R-FoM) achieves 45 fJ & sdot; K-2, illustrating the best-in-class performance compared to the resistor-based temperature sensors in the sub-65-nm process.

A 4-way 16GS/s two-step time-domain ADC with Vernierbased multipath Flash TDC architecture is reported. Benefiting from the proposed Vernier-based Multipath $\mathrm{T}_{\text {LSB }}$ Generator (VMTG) and the inherently tracking delay cells, this design achieves PVT robustness for time step ratios and gain between the two stages. Fabricated in 28 nm CMOS, this ADC achieves 35.3 dB SNDR and 51.2 dB SFDR with a Nyquist input at $16 \text{GS} / \mathrm{s}$ and it consumes 19.6 mW power, leading to a $25.7 \text{fJ} /$ conv.-step Walden FoM.

This paper presents a two-stage ultra-wideband (UWB) low noise amplifier (LNA) for 5G millimeter-wave (mm-Wave) applications in the 0.13-mu m silicon germanium (SiGe) technology. By employing T-coil with damped resistor as the load of a cascode stage, the bandwidth is considerably extended. The peak compensation between the two amplifier stages was also employed to broaden the operation bandwidth. The simultaneous wideband input power matching and optimum noise matching was achieved by utilizing dual L-type matching networks at the input. The proposed LNA demonstrates a simulated gain of 24 dB (+/- 1.5 dB), the bandwidth of 24.3 similar to 42 GHz (i.e. FBW similar to 53.4%), the noise figure (NF) ranging from 1.98 dB to 2.49 dB, with a corresponding peak FoM is 26.92 under 13.46 mW power consumption.

This paper reports an ultra-low voltage (ULV) relaxation oscillator (RxO) suitable for self-powered devices, designed with a pair of asymmetric swing-boosted (ASB) RC networks. This work enhances low-voltage operational capabilities and improves frequency stability and jitter performance. The RxO features a unique single amplifier configuration incorporated with a customized feedback mechanism that effectively compares the output voltages from the RC networks, substantially reducing jitter due to flicker noise. Additionally, we implement a Duty-Cycling Circuit (DCC) based on a DLL architecture to turn on the amplifier before the desired detection point, providing ample guard time and thereby reducing power consumption, which is essential for ultra-low power applications. The RxO also features a Replica Temperature Compensation Circuit (RTCC) to mitigate circuit delay. Fabricated in 65-nm CMOS, the RxO operates at 2.35 MHz with a minimal supply voltage of 0.5 V, achieving a period jitter of 390 ppm and line sensitivity of 17.4%, and an energy efficiency of 5.82 pJ/cycle. The device demonstrates significant improvements over existing ULV designs, achieving up to 60% reduction in power consumption while maintaining lower jitter levels.

Millimeter-wave (mm-wave) fractional-N (FN) PLLs with an rms jitter of <100fs are demanded by high-speed communication systems to realize precise channel selection [1] or accommodate different crystal frequencies [2]. Equipped with high-gain phase detectors (PDs), the FN sampling PLLs (SPLLs) [3], [4] and bang-bang PLLs (BBPLLs) [5]–[7] utilizing DTCs to cancel the quantization error (Q-error) from the multi-modulus divider (MMD) controlled by a delta-sigma modulator (DSM) have demonstrated superior jitter when synthesizing sub-15GHz outputs. In these FN-PLLs, the DTC is the most challenging block since it contributes substantial in-band phase noise (PN), and its nonlinearity increases the fractional (frac.) spur and noise folding. By directly driving the MMD with oscillator outputs, the required DTC range shrinks as the oscillator frequency increases, improving the DTC noise and linearity. However, at mm-wave frequencies, a prescaler is typically inserted to lower the MMD input frequency due to its limited speed, which enlarges the DTC range. In contrast, in an FN sub-sampling (SS) PLL, the Q-error can be canceled by delaying the reference (ref.) clock without resorting to the prescaler and MMD [8], restoring the small DTC range. In the FN SPLL or BBPLL, both the rising and falling edges of the oscillator output can be utilized to resample the MMD output, reducing the DTC range by half [4]. Regrettably, this DTC-range-reduction technique cannot be directly applied to an SSPLL. Furthermore, the SSPLL also suffers from a prolonged locking time due to the small capture range of the SSPD. Aided by a low-power TDC-based Type-I frequency-locked loop (FLL), the integer-N SSPLL in [9] archives $\text{sub}-\mu\mathrm{s}$ locking time. Nevertheless, this solution cannot be applied to locking a frac. channel since the frequency error $(\mathrm{f}_{\text{error}})$ after FLL locks is limited by the ref. clock frequency $(\mathrm{f}_{\text{ref}})$.

Single-inductor multiple-output (SIMO) DC-DC converters face the challenges of large inductor current, discontinuous charge to each output and poor self-regulation. This design proposes a switched-capacitor SIMO dual-path hybrid converter that can reduce the inductor volume and output ripple by taking the advantages of hybrid dual-path structure. The proposed path-sharing topology improves the transient response of the in-transient channel. This work, designed in a 0.18-mu m BCD process, reveals in the simulation that the cross-regulation is 20 mV/A and the self-regulation is 87 mV/A with a 1A load step. The simulated peak efficiency is 94.3% and maximum output ripple is 24 mV.

This article proposes an emulated peak/valley curve-assisted fast-transient buck converter that achieves almost one-cycle charge balance (OCB) load transient response. The previous OCB works require three-parameter calibration to mimic the output capacitor’s RLC, and high-speed inductor current sensor. Comparatively, this work fulfills a one-parameter calibration with reduced design complexity. Additionally, we employ a modified double adaptive bound (DAB) hysteretic control to enhance both transient detection speed and output voltage regulation. The prototype chip fabricated in a 180-nm BCD process, exhibits a measured maximum deviation-from-ideal (DFI) rate of 5.5% for output voltage undershoot/overshoot (US/OS) and recovery time under different load-step conditions. This implies that the transient performance is close to the theoretical optimum with the proposed OCB scheme. The measured load regulation is improved to 0.05%/A by the modified DAB scheme.

This paper presents a type-II sampling phase-locked loop (SPLL) that accelerates the locking process by exploiting a time-to-digital converter (TDC) based automatic frequency and phase calibration (AFPC) technique. The proposed AFPC accelerates the frequency acquisition by using a type-I loop to map the quantized phase error to the switched-capacitor (SC) control word of the voltage-controlled oscillator (VCO). The subsequent phase error after frequency locking is swiftly reduced within one TDC resolution by adjusting the division ratio of the multi-modulus divider (MMD) with little hardware expenditure. The proposed AFPC can guarantee a fast-locking time at different initial frequencies, which is insensitive to the variation of TDC resolution. This paper also contributes to a design strategy for the AFPC loop, e.g., the required frequency step of the SC and the TDC resolution, based on the analysis of the lock-in range of the SPLL. Fabricated in 28-nm CMOS with a core area of 0.15 mm(2), the 6.0-to-6.9GHz SPLL prototype using a reference (REF) clock of 100 MHz achieves a locking time of 0.62 mu s (62 T-REF) at an 880-MHz hopping frequency. At 6.5 GHz, the SPLL consumes 4.6 mW and measures an RMS jitter and REF spur of 99 fs and -71.6 dBc, respectively, corresponding to a jitter figure-of-merit (FoM(jitter)) of -253.5 dB.

>Fractional-N phase-locked loops （PLLs） are widely deployed in high-speed communication systems to generate local oscillator （LO） or clock signals with precise frequency. To support sophisticated modulations for increasing the data rate, the PLL needs to generate low-jitter output [1] . Since the output frequency of the fractional-N PLL is not an integer multiple of the reference clock frequency (f REF ),

High-efficiency, high-power-density, and fast transient response DC-DC converters are in high demand for consumer, automotive, and industrial applications. In recent years, many integrated hybrid converters have been developed to enhance efficiency and current density [1]–[4], in which the series-capacitor buck (SCB) converters [3] and [4] are particularly favored for their relative simplicity. Figure 21.9.1 (left) shows the Dickson SC hybrid Buck converter (DSC-HB) [5], which offers the advantages of inherent inductor current balance and reduced inductor voltage stress. To mitigate high-voltage device switching losses, converters with high voltage conversion ratios typically operate at lower switching frequencies, resulting in a reduced loop bandwidth (1/1 0-to-1/5 of the operating frequency) and requiring larger inductors. This constrains the inductor current slew rate during load transients and deteriorates the transient performance. This limitation is pronounced in DSC-HB topologies, where multiple output inductors cannot simultaneously increase current during transients. Previous works [6] and [7] addressed this limitation by simultaneously activating all inductors, achieving a 2x increase in the inductor current slew rate and improving the load transient performance. However, for load step-down transients, the inductor current's falling slew rate is still constrained by the low $\mathrm{V}_{\text{OUT}}$ and large inductance.

This study introduces a MEMS accelerometer equipped with an adaptive tuning system for an electrostatic anti-spring. As the input acceleration increases, the sensitivity of the adaptive MEMS accelerometer decreases to compensate for the measurement range. It leverages the benefits of both conventional open- and closed-loop accelerometer designs. Comprehensive theoretical analyses and experimental tests are conducted, showing consistency between theory and experimental results. In comparison to conventional MEMS accelerometer designs, this novel MEMS accelerometer demonstrates enhanced performance. With an actuation voltage of 15.4 V and under 0 g acceleration input, the sensitivity of the accelerometer improves from 1.28 V/g to 39.43 V/g, and the spring constant is reduced from 41.0 N/m to 1.38 N/m. The noise floor also decreases from 8628 ng/√Hz (at 100 Hz) to 279 ng/√Hz (at 100 Hz). The dynamic range enhances from 127 dB to 157 dB. Besides, a hybrid continuous-time interface is utilized to apply the actuation force on the sensing comb fingers. This approach not only simplifies the circuit design but also minimizes the required die area, power consumption. The combination of these features makes the novel MEMS accelerometer both highly sensitive and large measurement range, as a promising solution for various applications.

Humanoid robots have high potential to replace human labors for various tasks in the near future [1], [2]. As the robots are now very intelligent and smart, battery energy is the only thing that stops the robots from going further. A key issue in humanoid robots is that the battery pack (heart) is located in the main body while the energy is mostly consumed through legs and hands, demanding thick wires (strong blood vessels) to deliver power for the actuators (muscles). As illustrated in Fig. 9.9.1, the parasitic cable resistance would introduce large I2R conduction losses in a distributed electronic system, like an agile robot would need high current on their limbs. Thus, the thick and heavy wires account for a considerable portion of the total weight. To solve this issue, high-voltage (HV) power transmission is the key.