Developing large-scale integrated circuits starts with specifying the desired system behavior. While specifications must be precise and dependable for both design and verification purposes, traditional specifications rely on natural language documents and their human interpretation. This introduces two critical weaknesses: First, interpretation can be challenging due to vagueness and inherent ambiguity. Second, validating that a natural language specification expresses the intended behavior is hardly possible with deterministic methods. To tackle these challenges, we use a formal specification format, called the Universal Specification Format (USF), with unambiguous syntax and semantics. USF applies to the specification of general digital hardware and automatically generates formal properties for design verification. Still, it must be ensured that the formal specification—and thus the generated properties—correctly express the desired system behavior. In this paper, we present a novel code generator for behavioral simulation models to execute USF specifications and validate them against use cases. Moreover, we introduce and integrate runtime checks into the simulations that automatically detect inconsistencies and gaps in the specification. This methodology has been applied to industrial-strength hardware components and their formal specifications, demonstrating the effectiveness and industry-readiness of our behavioral simulation models and the automated runtime checks. We finally show that USF enables reusable code generators for both simulation-based specification validation and formal design verification.

Register-transfer level (RTL) generators are typically synthesis-agnostic. They use predetermined architectural parameters without considering how the synthesis tool’s behavior varies across constraints. Our framework enables constraint-aware generation by systematically characterizing how synthesis optimization creates regime-dependent trade-offs in design decisions. We characterize RV32I RISC-V cores across pipeline depths (2, 3, 4-stage) at five clock periods (0.5–5.0 ns), deriving a predictive framework that maps target clock period to optimal pipeline depth. The framework automatically identifies regime transitions by solving a constrained area-frequency optimization and generalizes to unseen frequencies through regime-based predictions. Validation on five unseen clock periods spanning all constraint regimes demonstrates that applying framework recommendations achieves significant area savings: up to 31.8% at ultra-tight constraints, up to 8.7% in the tight regime, and up to 12.2% at relaxed constraints compared to suboptimal architecture selections.

Runtime fault detection in modern processors is increasingly challenging due to technology scaling. Most existing mechanisms detect errors only at architectural boundaries, providing limited visibility into where faults originate or how they propagate within the pipeline. This paper presents the Non-Intrusive Unified Reliability Supervision Engine (NURSE), a distributed runtime supervision architecture composed of lightweight monitoring units deployed at processor pipeline stage boundaries. NURSE operates alongside the processor without modifying functional execution semantics, enabling continuous observation during normal operation. Each monitoring unit locally validates stage behavior and propagates compact instruction-aligned health metadata downstream, enabling distinction between locally induced faults, interconnect faults, and propagated faults. Evaluation on an in-order RISC-V processor demonstrates high coverage for pipeline interconnect faults and detection of execution anomalies with only 8.3% area and 19.9% power overhead in ASIC implementation. NURSE introduces an instruction-level diagnostic layer that improves fault observability for safety-oriented and resource-constrained systems.

The design productivity gap describes the growing disparity between the rate at which transistors can be manufactured and the rate at which they can be designed. As this gap has been continuously growing for decades, the size of teams required to design Systems-on-Chips (SoCs) and, as a consequence, the design cost increases as well. A further challenge is the growing verification effort of these SoCs. Furthermore, the amount of software to be developed continuously increases as well. One approach to raise productivity—at least for the digital part of an SoC—is the generation of Register-Transfer Level (RTL) and software code. Though different isolated generation approaches lack a structured approach for platform-specific collaterals. This demands reworking and adapting the generators or even reworking the code. This substantially decreases the potential benefit of using generators. This paper presents a novel, holistic Model-Driven Architecture (MDA)-based uniform approach for generating collaterals for SoCs, covering digital hardware and software, including both design and verification. As an additional contribution, this approach introduces an elaborated platform-independent model, as part of a two-stage approach of translating Platform-Independent Models (PIMs) into Platform-Specific Models (PSMs). This approach also leverages a Platform Model (PM) that steers the PIM-to-PSM translation. Finally, this approach utilizes models from one domain (e.g., HW) in another domain (e.g., SW) to reduce effort in expressing PMs and increase consistency between the different collaterals.

Hardware construction and code generation have been introduced to hardware development processes to cope with the increasing complexity of modern integrated circuits. Additionally, to maximize the reusability of such code generators, the Universal Specification Format (USF) provides a general formalism for high-level system specifications. USF models arbitrary hardware systems by their internal state and function set using a domain-specific expression language. However, it is this general modeling capacity of the USF formalism that also results in complex formal specifications, which can become tedious to write and prone to errors. Addressing these challenges, we present a specification workflow to simplify and harden the construction of valid USF models. It consists of two pillars: first, the parameterized construction of USF models simplifies system specification, and second, a novel constraint definition validates that the constructed specifications are correct. Moreover, we show that these constraints enable sweeping over a range of compliant configurations to automatically generate valid specification variants. Demonstrating the benefits of our workflow, we apply it to a selection of industrial hardware designs.

Rust has gained traction as a viable alternative to C within embedded software development, largely due to its focus on memory safety and advanced language abstraction. Building on these principles, we have extended an existing modelbased code generator, which is rooted in Model-Driven Architecture (MDA) concepts, to leverage the advantages of Rust. This method allows for generating C and Rust code from a single, platform-independent model, enhancing adaptability to changing requirements. The effectiveness of the proposed approach is evidenced by the successful generation of a dotproduct function compared to an equivalent implementation from the CMSIS-DSP kernel library in both C and Rust. In particular, this paper’s comparisons show a decrease in manual effort by 23-fold, improving the performance of previous approaches to streamline embedded software development.

The growing complexity of integrated systems demands the development of new and powerful design tools and methodologies. This paper proposes a novel design methodology for IP (Intellectual Property) design called Handshake-based Design, which addresses the substantial gap between the Register Transfer Level (RTL) and the algorithmic or IP layer. By decoupling separate building blocks using handshakes for communication and synchronization, this approach enables a modular and flexible design paradigm, where the emphasis lies on the functional behavior of components and the exchange of data between them, rather than on the precise timing and involved signals of these interactions. The methodology is based on two main concepts: interfaces and handshakes. Interfaces encapsulate multiple ports, providing a clear definition of signals and their parameterization, while handshakes are a simple yet powerful mechanism to facilitate data exchange between modules. Together, they allow designers to focus on the component functionality and data flow as well as synchronization separately by stepping away from single-cycle-thinking and bit signals. Aspects of the application of Handshake-based Design are demonstrated through the implementation of a RISC-V Processor, showcasing the method’s ability to facilitate a more structured and simplified design process.

The continuous drive toward the miniaturization of Integrated Circuits (ICs) is pushing the physical boundaries of device scaling. As transistor gate and interconnect dimensions shrink, several challenges emerge, including increased power density, thermal dissipation constraints, and quantum effects. Among these, electromigration—caused by the momentum transfer from high current densities to atoms—results in the displacement of material within interconnects, potentially leading to unintended open circuits or shorts. Similarly, manufacturing defects, environmental stresses, and aging effects further exacerbate these reliability issues, often manifesting as permanent faults, such as logic stuck-at-0 or stuck-at-1 conditions. To address these issues, Design-for-Test (DFT) infrastructure and Software-Based Self-Test (SBST) have been developed. While DFT is expensive in terms of area and performance, SBST is a cost-effective alternative that uses processor resources to test the chip. However, generating efficient test patterns with high fault coverage remains a challenge. In this paper, we propose a technique for optimizing testing software for SBST targeted towards specific components with uniform structures such as a RISC-V Register File. The method requires knowledge of the component structure and function, and uses fault simulation to verify fault coverage. The method achieved a fault coverage of 99% of functionally testable faults in the Register File.

Register-Transfer Level (RTL) generators streamline hardware design but often produce generic designs that fail to leverage platform-specific resources, resulting in suboptimal performance or non-deployable implementations. This paper introduces a novel model-driven methodology that enhances RTL generation by seamlessly adapting to the target platform's unique capabilities. By incorporating platform-specific constraints, our approach automates the mapping of RTL constructs to optimized resources, overcoming the limitations of platform-agnostic designs. We validate the methodology through the implementation of a RISC-V-based System-on-Chip (SoC) on an AMD Zynq UltraScale+ MPSoC board. Experimental results demonstrate remarkable improvements, reducing lookup table (LUT) usage by up to 97%, flip-flop (FF) usage by up to 99%, achieving over 3x higher maximum frequency, lowering power consumption by approximately 10%, and reducing design implementation run time by up to 94% compared to platform-agnostic designs.

Shifting toward higher levels of abstraction is crucial for addressing the growing productivity gap in hardware design and verification. To this end, the Universal Specification Format (USF) extends Instruction Set Architecture (ISA) concepts from processor design to general digital design, providing a unified framework for formal specification and automated code generation. Still, the applicability of the USF specification format to general digital systems has yet to be thoroughly demonstrated. In this work, we apply USF to diverse hardware components, including structural modules, control-flow-driven designs, and communication protocols. We also show how conventional Intellectual Property (IP) parameterization of these USF models enables the efficient specification of multiple design variants. Our evaluation demonstrates that USF successfully captures the behavior of the selected component types while maintaining specification clarity and enabling efficient code generator reuse. We establish the broad applicability of ISA-inspired specification formats like USF beyond their original processor-centric domain, validating their utility for IP specification and automated verification.

Digital division is a pivotal operation in a number of domains, such as scientific computation, cryptography, digital signal processing, and machine learning, and has been broadly researched in the past decades. However, the increasing demand for efficient digital systems has emphasized the design of digital dividers with more stringent area and power costs without excessively compromising their performance. One option to achieve this is to implement Single Instruction Multiple Data (SIMD) dividers capable of exploiting the abundance of data-level parallelism, which is naturally present in common tasks such as stream processing, matrix normalization, and vector scaling. In this paper, we propose the designs of four configurable integer dividers capable of sustaining both Single Instruction Single Data (SISD) and SIMD computations, targeting different levels of performance and efficiency. Compared to one of the state-of-the-art integer dividers, our most efficient SIMD divider shows a 54% smaller area and 30% lower power consumption. Furthermore, we propose a novel technique which can reduce n-bit divisions to smaller (n - m)-bit ones, yielding a peek speedup of 15% when implemented in one of our proposed dividers.

Register-Transfer Level (RTL) generation is foundational to hardware design, converting high-level specifications into synthesizable descriptions for physical implementation. Conventional RTL generators produce platform-agnostic designs to enable flexibility across diverse targets (e.g., FPGA or ASIC), however this approach is problematic for designs with technology-specific components (e.g., memory macros), where generic constructs—suitable for simulation and verification—fail to leverage native hardware resources, leading to either non-implementable designs or inefficient synthesis and degraded power, performance, and area (PPA) metrics. Extensive manual adaptations are thus required, eroding automation benefits and widening the design productivity gap. This paper proposes a cross-platform methodology that automates the generation of RTL code and constraints tailored to both ASIC and FPGA platforms, enabling optimal native resource utilization. Applied to a RISC-V subsystem, it enables seamless synthesis and implementation across targets, forming an end-to-end workflow from specification to deployment. Evaluations on an AMD Zynq UltraScale+ FPGA and a 22 nm ASIC process demonstrate substantial improvements: up to 3.66× higher maximum frequency, 3.44× area reduction, 5.99× power savings, and 18.80× faster implementation run times compared to platform-agnostic baselines, affirming its robustness for modern embedded systems.

The gap between design and implementation has long been a bottleneck in hardware development, with Register-Transfer Level (RTL) generation often neglecting the physical implementation constraints that can make or break a design. This paper presents a novel approach to Platform-Aware RTL Generation, bridging the gap between design and implementation by incorporating platform-aware considerations into the RTL generation stage. Our approach enables the creation of implementation-aware RTL code that takes into account the physical constraints of the target platform, such as timing, power, and area. By doing so, we reduce the number of design iterations and improve the overall efficiency of the hardware development process. The key to our approach is a flexible engine that interprets platform models and modifies design models through a set of fundamental editing operations, resulting in RTL code that is tailored for the target platform. We demonstrate the effectiveness of our approach through qualitative analysis and quantitative results, showing a significant 73% reduction in code generation effort for industrial-grade designs. By bridging the gap between design and implementation, our Platform-Aware RTL Generation flow has the potential to revolutionize the hardware development process, enabling faster time-to-market, improved design quality, and reduced development costs. Index terms—Model Driven Architecture, RTL generation, Platform-Aware RTL Design, Deployment Platform Constraints, Technology-Specific Optimization, Design for Test, Safety.

Floating-point representations enable finer granularity of computations, improving the overall accuracy of ML models. Approximate computing techniques using variable bit-width can be employed to reduce the computational complexity of training algorithms while maintaining an acceptable level of accuracy. In this work, we propose FPUGen: a framework to generate custom floating-point (FP) fused multiply-add (FMA) accelerators. The accelerators have several architectural highlights such as: (a) Reconfigurable FP-FMA units for any mantissa and exponent size, (b) Dynamic precision FMA (DFMA) support for one SP-32, two TF-32, two HP-16, or three BF-16 operations in parallel, (c) Rounding logic for dynamic precision and (d) pipelined/non-pipelined FP-FMA architecture support. We note that choosing BF-16 over DP-64 and SP-32 saves energy by 5.73x and 2.56x respectively on an FPGA. Our proposed DFMA-V2 architecture is 1.49x more resource efficient, has 3.85x better throughput, and is 1.71x more energy efficient compared to the baseline design (DFMA-V1) due to the pipelined and resource-sharing architecture. It achieves a maximum throughput of 56.10 GFLOP/s on the ZCU104 FPGA, which is 5.8x higher than the baseline design.

A key challenge for Deep Neural Network (DNN) inference on resource-constrained edge devices is the high energy consumption caused by frequent memory accesses for parameters. While our previous research has demonstrated the efficacy of data compression for weights, this paper extends our approach to include on-the-fly compression and decompression of activations. We propose a comprehensive hardware solution comprising two main components: a Golomb-Rice (GR) compression system and an Output Activation Processing Module (OAPM). The GR system provides an efficient activation compression mechanism, while the OAPM enables dynamic data-format capabilities for handling activations. Additionally, we present an enhanced Input Activation Extract Module (IAEM) with an integrated decompression unit and dynamic activation processing capabilities. When integrated with an industry-strength Neural Network accelerator and evaluated using the Anomaly Detection (AD) TinyML benchmark, our lossless compression system achieved a 2.3x compression ratio, reduced memory bandwidth usage by 49.28%, and improved inference speed by 10%.

The increasing complexity of modern hardware designs necessitates shifting from traditional Register-Transfer Level (RTL) abstractions to higher-level modeling approaches. One of these approaches, the Universal Specification Format (USF), based on metamodeling and embedded in the Python programming language, enables the uniform expression of digital hardware systems’ functional and temporal behavior. While USF models are inherently static, conventional hardware development heavily relies on simulation for tasks ranging from early validation and debugging to dynamic verification and virtual prototyping. Bridging the gap between static specifications and dynamic development needs, we present a novel code generation approach that transforms USF models into executable behavioral models. Our method employs static scheduling with user-defined parallelism, producing executable and synthesizable models for cycle-accurate hardware simulation and emulation. Applying our approach to both the simulation and synthesis of a concrete component specification and variants hereof demonstrates the feasibility and reusability of the proposed code generator.

Formal specification has been introduced to the development of modern digital hardware systems, alleviating the ambiguities and misinterpretations common with informal, natural language specifications. The Universal Specification Format (USF) is an existing approach to formal specification, which is used to prove the correctness of Register-Transfer Level (RTL) designs. Still, using such formal specifications as verification references requires validating that the specifications themselves are correct, which is often performed dynamically through usecase simulation. To fulfill the need for dynamic evaluation, we present a model-driven code generator that translates static USF specifications into untimed software simulations. The translation preserves hardware semantics by reordering operations and utilizing untimed, event-based interface handshakes. Our application to different hardware components, including a RISC-V processor, demonstrates the versatility and reusability of the code generation approach. Due to the abstract nature of the generated models, they execute between $1.5-4.5 \times$ faster than RTL simulations and can be constructed early in the design process without concrete timing information.

Adopting Large Language Models (LLMs) has recently gained prominence in various natural language processing tasks, including in the electronic design automation industry. As an inverse approach, this work considers using LLMs to process formal hardware models and generate human-readable design documentation hereof. We automatically preprocess formalized system-level hardware specifications to create prompts for LLMs. Based on these prompts, an LLM generates an extensive, human-readable explanation of the system. While this workflow has already shown to be viable as a concept, technical errors and style issues are the prevalent restrictions for wide-scale application. Addressing these issues, this paper presents a selection of advanced post-processing and prompt engineering techniques to improve the quality of the LLM-generated documentation. Applying our extended workflow to a set of hardware components demonstrates that the incorporated methods are especially effective in ensuring the documentation’s correct formatting and style conformity. Although occasional technical errors still occur, we observe a significant reduction in manual revision efforts, with 46.4% of the generated documentation not requiring any further changes.

The push to support artificial intelligence in embedded systems introduces new challenges regarding software support of specialized hardware. The RISC-V instruction set architecture offers a promising platform for accelerators for said AI applications through custom instructions. Integrating these instructions into existing software codebases poses significant challenges, including manual adaptations and limited compiler support. This paper introduces a novel approach that generates hardware-optimized code utilizing custom instructions defined by a platform model. This method enhances the reusability of code and leverages design artifacts from the hardware design process to optimize the generated software in both C and Rust by generating intrinsic support for custom instructions through inline assembly. If the underlying platform does not allow the utilization of the specified custom instruction, an alternative implementation with optional global side effects is generated instead of the intrinsic. Thus, it expedites development by minimizing manual coding efforts and facilitates the seamless integration of hardware accelerators. An exemplary implementation of a matrix multiplication utilizing a custom multiply-accumulate instruction presented in this paper highlights the efficiency provided by this approach. Measurements based on this implementation show a reduction of the executed instructions by up to 75% while also achieving a 5-fold theoretical reduction in manual effort.