Most evaluations of External Memory Module assume a static setting: memory is built offline and queried at a fixed state. In practice, memory is streaming: new facts arrive continuously, insertions interleave with retrievals, and the memory state evolves while the model is serving queries. In this regime, accuracy and cost are governed by the full memory lifecycle, which encompasses the ingestion, maintenance, retrieval, and integration of information into generation. We present Neuromem, a scalable testbed that benchmarks External Memory Module under an interleaved insertion-and-retrieval protocol and decomposes its lifecycle into five dimensions including memory data structure, normalization strategy, consolidation policy, query formulation strategy, and context integration mechanism. Using three representative datasets LoCoMo, LONGMEMEVAL, and MemAgentBench, Neuromem evaluates interchangeable variants within a shared serving stack, reporting token-level F1 and insertion/retrieval latency.Overall, we observe that performance typically degrades as memory grows across rounds, and time-related queries remain the most challenging category. The memory data structure largely determines the attainable quality frontier, while aggressive compression and generative integration mechanisms mostly shift cost between insertion and retrieval with limited accuracy gain.

Stream Learning (SL) requires models that can quickly adapt to continuously evolving data, posing significant challenges in both computational efficiency and learning accuracy. Effective data selection is critical in SL to ensure a balance between information retention and training efficiency. Traditional rule-based data selection methods struggle to accommodate the dynamic nature of streaming data, highlighting the necessity for innovative solutions that effectively address these challenges. Recent approaches to handling changing data distributions face challenges that limit their effectiveness in fast-paced environments. In response, we propose StreamFP, a novel approach that uniquely employs dynamic, learnable parameters called fingerprints to enhance data selection efficiency and adaptability in stream learning. StreamFP optimizes coreset selection through its unique fingerprint-guided mechanism for efficient training while ensuring robust buffer updates that adaptively respond to data dynamics, setting it apart from existing methods in stream learning. Experimental results demonstrate that StreamFP outperforms state-of-the-art methods by achieving accuracy improvements of 15.99 compared to baseline models across varying data arrival rates, alongside a training throughput increase of 4.6x.

Efficient dynamic graph processing is critical for real-time applications. Recent systems utilize hybrid layouts combining Packed Memory Array (PMA) and Compressed Sparse Row (CSR) structures to balance updating and computing efficiency. However, these systems face key challenges, including costly global copying and traversal during reconstruction, which in turn induce excessive costly rebalancing processes during graph updating, limiting performance under intensive updates. To mitigate these, existing solutions either compromise cache efficiency by relaxing memory contiguity or apply OS-level techniques without exploiting graph structural properties, leaving large optimization space unexplored. In this paper, we propose GRACE, a lightweight extension for PMA-based CSR systems that leverages graph structural properties to improve reconstruction and support efficient updates without sacrificing layout contiguity. Specifically, GRACE incorporates 1) a propertyguided reservation strategy that partitions the PMA into regions and applies tailored methods, minimizing copying and traversal during reconstruction while providing optimized layout for rebalancing, and 2) a cousin-aware rebalancing strategy that assesses the impact of the vertices and confines rebalancing to smaller ranges by exploiting cousin segments of PMA tree, reducing redundant relocation during insertion. We implement GRACE as a modular plugin atop representative dynamic graph processing systems, including PPCSR, Terrace, and VCSR. Experimental results show that GRACE effectively accelerates their reconstruction and achieves substantial improvements in graph updating efficiency while maintaining comparable computing performance.

Retrieval-Augmented Generation (RAG) improves the factuality and timeliness of large language model outputs by incorporating external knowledge during inference. Recent systems accelerate RAG by precomputing and caching documentside Key-Value (KV) pairs, eliminating repeated encoding of long retrieved documents. However, this centralized KV-reuse paradigm introduces two fundamental bottlenecks: (1) massive off-chip KV transfers, since large-scale document KVs must reside in host memory and be moved to the device at query time, and (2) severely underutilized compute resources, as short queries yield skinny GEMMs during prefilling and memory-bound GEMVs during decoding. We address these limitations with Meridian, a decentralized RAG system built on two key components. First, we introduce document attention decomposition, which replaces centralized KV processing with a distributed execution model: document-side $K$ and $V$ matrices are sharded across PIM-enabled memory modules, and each device computes attention over its local shard, producing compact partial summaries that are merged through a lightweight global aggregation step. This sharply reduces offchip KV movement. Second, to improve compute efficiency, Meridian incorporates a PIM-based accelerator co-designed with the decomposition mechanism. It provides a resource-conscious in-memory compute substrate for accelerating skinny GEMM and nonlinear operations, and employs a coordination-aware hybrid scheduler to sustain efficient intra-device execution and scalable inter-device parallelism. Evaluations show that Meridian achieves average throughput improvements of 5.36×/6.64×/3.98×/3.32×/3.91× and latency reductions of 4.30×/5.34×/3.31×/2.73×/2.79× over TurboRAG, BlockAttention, CENT, PAPI, and HeterRAG, respectively.

Transformer-based large language models (LLMs) exhibit remarkable generative capabilities, but their inference throughput is limited by the autoregressive decoding process, which generates only one token per iteration. Speculative decoding mitigates this bottleneck by using a lightweight draft language model (DLM) to generate multiple draft tokens, which are then verified in parallel by a more accurate target language model (TLM). To accommodate the differing computational patterns of the DLM and TLM, prior work has leveraged heterogeneous systems combining xPUs and processing-in-memory (PIM) units to offload compute- and memory-intensive operators, respectively. However, existing systems often adopt a fixed draft sequence length, leading to excessive rejection of draft tokens during verification-especially under large-batch scenarios-resulting in redundant computation and reduced efficiency. This paper proposes a runtime adaptive draft length adjustment technique that dynamically tailors the draft length for each request by monitoring cumulative acceptance probabilities, thereby minimizing the generation and verification of invalid tokens. Yet, integrating adaptive draft lengths into existing PIM-enabled heterogeneous systems introduces two new challenges: (1) sequential execution of the DLM and TLM becomes inefficient due to synchronization bubbles caused by request-wise variability in draft lengths, and (2) static operator mappings become suboptimal as draft length variability alters operator arithmetic intensities dynamically. To address these issues, we introduce SADDLE, a PIM-enabled heterogeneous system designed to exploit adaptive draft lengths effectively. SADDLE incorporates two key mechanisms: (1) an asynchronous speculative decoding pipeline that decouples DLM prediction and TLM verification to reduce idle time, and (2) an arithmetic intensity-aware operator scheduler that dynamically assigns operators to the most suitable hardware units. Experimental results show that SADDLE achieves average speedups of 2.88x over a state-of-the-art GPU-only solution and 1.71x over the best-performing GPU+PIM baseline.

Memory disaggregation provides key-value stores larger memory capacity at low cost. Emerging compute express link (CXL) enables efficient memory disaggregation. It, however, dramatically slows down the system performance as disaggregated memory accesses are considerably slower than local memory accesses. This article presents Nemo, a near-memory accelerator architecture for CXL-based memory-disaggregated key-value stores. To address the CPU-accelerator latency, Nemo provides a set of new techniques that enable fast task dispatch, cache-conscious task offloading without CPU modifications, and versatile support of custom data types. We evaluate Nemo on the core in-memory index of RocksDB and six widely used in-memory indexing microbenchmarks under YCSB query workloads. Nemo reduces up to 91.8% of slow disaggregated memory accesses, achieves a 2.05× average speedup over the CPU-only configuration, and accelerates key-value stores by up to 4.5×.

\noindent Hypergraph pattern mining (HPM) is a key analytical primitive for discovering higher-order relationships in complex data. Despite decades of algorithmic progress, existing systems remain far from saturating available compute resources, as the memory-bound and irregular nature of hypergraph workloads severely constrains sustained throughput. Our empirical characterization shows that even state-of-the-art (SOTA) HPM systems achieve only a small fraction of their theoretical peak performance on real workloads. In this paper, we propose Octopus, the first full-stack hardware-software co-designed system for accelerating HPM on practical processing-in-memory (PIM) hardware. Octopus targets UPMEM, an emerging commercially available PIM platform that integrates thousands of lightweight in-memory compute units within standard DRAM modules. To fully exploit UPMEM's massive parallelism and bandwidth potential while addressing its stringent architectural constraints, Octopus introduces two tightly integrated components: (i) an inter-DPU coordination framework that orchestrates compact data partitioning and balanced workload distribution across thousands of DPUs, and (ii) an intra-DPU mining engine that enables efficient hyperedge-level candidate generation and asynchronous multithreaded execution. We evaluate Octopus on a real UPMEM platform using diverse real-world hypergraph workloads. Experimental results demonstrate up to 55.37×, 19.80×, 1033.89×, and 795.08× speedups over SOTA solutions HGMatch, OHMiner, Pangolin, and PimPam, respectively.

Random walks have become a widely used tool for graph analysis.Unlike traditional first-order random walks,second-order random walks can better capture high-order structures in data by considering recent walk history.However,existing solutions face two major issues.First,they fail to fully account for the dependencies among graph blocks,resulting in that walkers with high correlation cannot be updated in time and thus reducing the I/O utilization of these blocks.Second,most systems handle random walk updates on a per-walker basis,causing repeated loading and computation of the same graph data,which in turn lowers update efficiency.To cope with these issues,this paper proposes an out-of-core graph processing system DSWalker for second-order random walks.It significantly reduces the data access cost of the existing random walk system by prioritizing the loading of graph block combinations that can activate more walkers,and by exploiting the data access similarity among concurrent walkers,thereby effectively improving the walk update efficiency and overall system performance.Specifically,DSWalker designs a novel dynamic I/O block scheduling strategy,which enables the graph data to be loaded in an optimal I/O accesses and effectively reduces the redundant data loaded into the memory.Meanwhile,DSWalker regularizes the update order of the graph partitions for concurrent walkers,enabling them to share access to the same graph structures in the cache,so as to amortize the data access overhead.Compared with SOWalker,the most advanced dynamic graph processing system for monotone graph algorithms,DSWalker speeds up dynamic directed graph processing by an average of 2.2 times.

Mining temporal motifs in temporal graphs is essential for many critical applications. Although several solutions have been proposed to handle temporal motif mining, they still suffer from substantial inefficiencies due to significant redundant graph traversals and fragmented memory access, both caused by irregular search tree expansions across different motif matching tasks. In this work, we observe that data accesses issued by these tasks exhibit strong spatial similarity and temporal monotonicity. Based on these observations, this paper proposes an efficient data-centric temporal motifmining system DTMiner, which introduces a novel LoadExplore-Synchronize (LES) execution model to efficiently regularize data accesses to the common temporal graph data among different tasks. Specifically, DTMiner enables the temporal graph chunks to be sequentially loaded into the cache in temporal order and then triggers all relevant tasks to explore only these loaded data for search tree expansions in a fine-grained synchronization mechanism. In this way, different tasks can share the graph traversal corresponding to the same chunks, while fragmented memory accesses are restricted to the graph data residing in the cache, significantly reducing data access overhead. Experimental results demonstrate that DTMiner achieves 1.14x-11.98x performance improvement in comparison with the state-of-the-art temporal motif mining solutions.

Shared state increasingly shapes both performance and failure behavior in streaming, serving, retrieval, and continual-learning systems. Existing studies, however, often isolate access control, hardware-aware execution, memory management, and long-horizon updates. The review organizes this literature around three coupled dimensions: state access and scheduling, state-aware execution, and state evolution and reuse. Across these dimensions, the literature is synthesized through a common scaffold: state object, control surface, coupling path, evaluation boundary, and unresolved contract. This comparison identifies recurring anti-patterns and informs a contract-oriented blueprint and disturbance-aware evaluation agenda. Taken together, the evidence characterizes state management as a runtime control problem.

Efficient processing of streaming graphs is crucial to improve system performance. Due to the highly irregular and frequent access to data in streaming graph processing, existing cache management methods are difficult to accurately predict cache behavior, resulting in serious cache misses. To address the issues, we propose CEGraph, an efficient cache management approach for streaming graph processing. Specifically, for graph data, we propose a cache replacement policy based on vertex importance. This policy accurately evaluates the importance of vertices in the incremental processing of streaming graphs from our proposed three factors: 1) the association degree of affected state of a vertex; 2) the path distance of a vertex; and 3) whether a vertex will be updated. Vertices with high importance are identified and kept in the cache to reduce cache thrashing. Experimental results reveal that compared with LRU, DRRIP and Grasp, CEGraph reduces the last-level cache (LLC) misses by an average of 22.93% (maximum 34.27%), 20.87% and 11.91%, respectively. Compared with the state-of-the-art cache management method P-OPT, CEGraph reduces the LLC misses by 6.46% on average, therefore demonstrating the effectiveness of CEGraph.

Programmable data planes enable in-network computing functions in cloud fabrics, but their prevailing compileand- redeploy workflow creates a reconfiguration bottleneck: application logic remains coupled to a target-specific pipeline layout, updates can require disruptive base-pipeline redeployment, and switch memory is reserved statically at compile time. We propose P4asm, an eBPF-inspired runtime-virtualization framework for supported in-network computations. P4asm installs a fixedparser P4 runtime that interprets compact virtual-instructionset bytecode and manages application code and state in a logical heap. The controller can then install, replace, and reclaim supported application logic without redeploying that fixed base runtime. We implement the framework on the BMv2 behavioral model to validate its functional design. Our BMv2 testbed results provide prototype-level evidence rather than ASIC claims. In representative traces and request replays, P4asm reduces application code size by 13× to 25×, avoids reboot outages during logic injection, keeps the critical version switch step within 10 ms to 20 ms across three sampled update cases, and preserves bounded behavior under loss and controller disconnects. The workload and ablation figures are reported as fixed operatingpoint summaries of these testbed runs.

Modern out-of-core random walk systems partition large disk-resident graphs into blocks and use walkers to efficiently scale graph processing. However, our study reveals a critical inefficiency: while most walker updates are processed efficiently, a small fraction of remaining walkers incur disproportionately high block I/Os, accounting for over 75% of total block I/O time. This performance bottleneck stems from static in-memory block layouts, which lead to excessive loading of irrelevant data during late-stage walker updates. To address this, we introduce LocWalker, a storage system that combines algorithmic and hardware innovations to optimize I/O efficiency for out-of-core random walks. At the algorithmic level, LocWalker specifically optimizes the last remaining few walkers processing through a skeleton-based walker updating scheme and a bounded breadth-first search (BBFS)-based block shrinking mechanism, both leveraging temporal and spatial locality to reduce the number and size of block I/Os per iteration during the iterative random walk process. Architecturally, LocWalker integrates a hardware-accelerated block provision engine on a computational SSD to minimize additional computational overhead introduced by our innovative features. High-level APIs enable easy integration with existing systems. Evaluated against SOWalker, GraphWalker, and NosWalker with a Samsung SmartSSD, LocWalker achieved substantial I/O time reductions (1.82 × to 11.06 ×) and overall performance improvements (1.44 × to 5.43 ×).

NVM provides a more generalized high-density memory media with DRAM-like performance and non-volatile nature to provide persistent data accesses to computing devices. Due to the poor write tolerance of NVM, wear-leveling strategies are essential in NVM. We find that the remapping table accesses become a neglected performance bottleneck when deploying wear-leveling strategies in NVM controllers, and contiguity-based CPU address mapping caching optimization strategies cannot be adapted due to the randomized mappings introduced by wear-leveling strategies. In this paper, we present RTCache, an efficient caching mechanism designed to accelerate access performance of the wear-leveling remapping table in NVM controllers. We propose a two-level mapping cache to enhance the cache utilization, consequently improving the cache hit ratio. Notably, RTCache incorporates a victim cache to improve the efficiency of RTCache for discretely accessed pages. Furthermore, RTCache adopts a cache-friendly remapping table memory structure, mitigating the challenges posed by access amplification due to RTCache misses. Experimental results show that RTCache can significantly improve the performance of NVM with wear-leveling strategies, and the negative impact on the system performance is reduced to an acceptable level.

Existing streaming graph processing solutions typically leverage incremental computation, which relies on an iterative process with two basic phases of refinement and recomputation, to reduce redundant computations while preserving accuracy. However, these existing efforts still suffer from serious problems of irregular memory accesses and sequential tag propagation arising in the refinement phase, which severely underutilize many-core processors. To cope with it, we propose GraphPro, a hardware-accelerated incremental computation engine that augments many-core processors to enable efficient streaming graph processing. GraphPro is specialized in accelerating the refinement phase and performing the recomputation phase, while the host CPU cores are responsible only for handling graph updates (e.g., edge/vertex additions and deletions). Specifically, GraphPro incorporates two key mechanisms: (1) a redundancy-aware dependency storage format that transforms most irregular memory accesses induced by affected vertex identification into sequential accesses while minimizing additional storage overhead, and (2) a lightweight dependency maintaining scheme that leverages metadata to reduce maintaining overhead and overlaps dependency maintaining with graph update to further hide latency. Experimental results show that GraphPro achieves speedups of 8.23 ×∼ 17.52 × over the state-of-the-art CPU-based system GraphFly and 1.30 ×∼ 1.82 × over the best-performing hardware accelerator TDGraph.

Hyperdimensional computing (HDC) is a human brain-inspired computing paradigm that processes neural activity patterns with high dimensional vectors. Existing HDC accelerators usually utilize different hardware architectures to process encoding phases and comparison phases of HDC applications separately. They are unable to adapt to dynamic workloads for various datasets, resulting in resource underutilization. In this article, we propose a resistive random access memory (ReRAM)-based HDC accelerator called ReHDC for general HDC. We abstract the computing paradigms in encoding and comparison phases, and provide uniform primitive operators to efficiently process these two phases with the same hardware architecture. In the unified processing engine, ReHDC utilizes analog crossbar arrays to accelerate accumulation operations, and digital crossbar arrays to speed up high-dimensional element-wise operations (xor). Experimental results show that ReHDC can accelerate the HDC training by 69.4x and 1.93x, and can also improve the energy efficiency by 51.5 x and 2.2x , compared with NVIDIA Tesla P100 GPU and the ReRAM-based HDC accelerator DUAL, respectively. Moreover, the performance speedup and energy efficiency for HDC inference are similar to that of HDC training.