Quantum computing is quickly evolving from the era of quantum advantage to quantum utility, thereby enabling the formulation and implementation of large-scale, application-driven quantum algorithms. However, existing approaches often incur prohibitive sampling and reconstruction overheads due to their lack of sensitivity to application structure and device heterogeneity. DAScut proposes a Density-and-Structure-aware circuit cutting framework that exploits fidelity-aware circuit to device mapping and isomorphism awareness to reduce execution and reconstruction costs. Experimental results using selected benchmark quantum algorithms demonstrate that DAScut reduces redundant sub-circuit execution by up to 52

Next-generation multi-dimensional WANs require intelligent resource management across terrestrial, aerial, and space infrastructures under dynamic and heterogeneous conditions. Network slicing enables applicationaware resource allocations across the network, however, the heterogeneity in application resource requirements and the dynamicity of environments make resource management a complex activity. This paper proposes a comprehensive cross-stratum resource management framework, AIM-CORE, that leverages artificial intelligence to maximize resource allocation, ensure Quality of Service compliance, and maintain system resilience across three-dimensional network architectures. AIM-CORE addresses dynamic network conditions, heterogeneous resource characteristics, and cross-stratum security challenges to enable autonomous support for mission-critical applications.

KoHPCG is a performance-portable HPCG benchmark program developed using the Kokkos programming model. The Reference HPCG benchmark is constrained by memory-bound kernels that restrict performance across various architectures. This paper details a thorough implementation of core HPCG kernels, including Dot Product (DDOT), WAXPBY, Sparse Matrix Vector Multiplication (SpMV), Symmetric Gauss-Seidel (SymGS), and Multigrid (MG), utilizing the Kokkos::Views, parallel constructs, execution and memory space abstraction. Evaluated on Intel Xeon Phi (KNL) and Xeon Skylake (SKL) processors with a maximum of 16 nodes, KoHPCG achieves significant performance improvement up to 11.7x acceleration in MG on SKL, alongside a 17.3x MG improvement on KNL. The overall HPCG performance increases by as much as 3.2x on SKL and attains 4.1x on KNL compared to the Reference HPCG implementation, on problem sizes of 192(3) and 160(3) on SKL and KNL, respectively. Furthermore, on a larger problem size of 320(3), KoHPCG attains an overall HPCG performance improvement of 5.1x on SKL. In addition to the overall performance improvement in HPCG, we reported the kernel-level performance that exposes the little and no performance improvement in SpMV and WAXPBY respectively, and increased memory consumption by using the Kokkos data structure, thereby highlighting further optimisation opportunities for future work.

With rapid advancements in AI, GPU accelerator technology is evolving, leading to an increase in heterogeneous computing nodes within data centers. This necessitates schedulers that can identify and efficiently manage diverse resources to dynamically meet application demands. For latency-sensitive tasks such as deep learning inference, imprecise GPU scheduling can cause resource interference, degrading both application performance and overall GPU utilization. The rise of NLP and large language models (LLMs) has heightened the focus on balancing throughput and latency. However, dynamic loads on specific resources can lead to performance degradation due to head-of-line blocking. Consequently, proactive resource management is essential to reduce costs while ensuring quality of service (QoS) and maintaining energy efficiency. This paper introduces OLTunes, a cluster-level scheduling system for deep learning inference models that integrates streaming and batch methods to efficiently manage both online and offline models. By leveraging FM-FTML, an online learning technique, OLTunes optimizes runtime environments and resource allocation to meet user SLAs through prediction and optimization. It groups tasks based on their characteristics and model variants to minimize interference, ensuring complementary affinities. It also automatically adjusts resources and configurations to improve performance and reduce resource fragmentation. Performance experiments on a heterogeneous GPU cluster demonstrated a 58

Efficient GPU resource sharing is critical in dynamic cloud-based environments, particularly for lightweight HPC applications and Small Language Models, which demand partial GPU resources for execution. However, traditional scheduling frameworks fail to address intra-GPU and inter-node resource fragmentation and dynamic placement challenges arising from the heterogeneity in each application’s resource demand and job completion times. This leads to resource under-utilization and scheduling delays in GPU clusters. This paper introduces Dyna-P, a novel scheduling framework designed to dynamically adjust GPU partitions to minimize resource fragmentation while improving system throughput and Makespan. Dyna-P proposes a Reconfiguration Last Placement policy which recognizes that workloads consisting of lightweight applications can benefit more from uninterrupted execution. Experimental results demonstrate that Dyna-P improves average throughput by up to 14.7

Graphic Processing Units (GPUs) are gradually becoming mainstream computing resource for efficient execution of applications both on-premises and in the cloud. Currently however, most HPC applications are unable to leverage the large computing capabilities they provide leading to issues of resource under-utilization. Various GPU sharing approaches have been proposed which leverage either software or hardware level mechanisms like MPS or MIG in NVIDIA GPUs. However, combining both the software and hardware level technologies in an effort to mitigate resource under-utilization issues is yet to be fully explored. In this paper, we conduct a case study on scheduling memory intensive and compute intensive applications on an NVIDIA A30 GPU. We compare the performance when using only hardware level sharing mechanisms and when using both hardware and software level mechanisms. We observed that by combining both mechanisms, we improved total execution times by up to 14% for a single run whilst improving peak bandwidth utilization by about 39% for SCAN application.

Graphic Processing Units (GPUs) are known for the large computing capabilities they offer users compared to traditional CPUs. However, the issue of resource under-utilization is becoming more apparent as more and more applications are unable to saturate modern GPUs which have even higher processing capabilities. While concurrency mechanisms like hardware partitioning have resulted in better utilization compared to deployments without sharing, the issue of resource under-utilization still persists even in deployment scenarios where applications are executed on the smallest GPU partitions of modern GPUs. Software partitioning on the other hand, does not guarantee isolation during executions leading to issues of interference and consequently limiting the number of applications which can be run concurrently. Leveraging both software and hardware resource partitioning schemes in an effort to mitigate resource under-utilization issues is yet to be fully explored. In this paper, we evaluate the predictions of a proposed linear regression model relative to actual executions. The results of our experiments show that whilst our approach accurately estimates performance for sharing differently-sized GPU partitions among diverse applications based on each application’s characteristics, it also improves utilization and reduces resource wastage.

Cache management is a significant aspect of executing applications on GPUs. With the advancements in GPU architecture, issues such as data reuse, cache line eviction and data residency are to be considered for optimal performance. Frequency of data access from global memory has significant impacts on the performance of the application with increased latencies. However, the L2 cache data residency feature by NVIDIA promises to reduce the overheads associated with frequent data accesses. Through the information extracted from static profiling analysis, we quantitatively analyzed the frequency of data reuse by threads to determine whether an application has frequent data accesses or not. We also estimated the size of access policy window from which persistent data should be cached to avoid stalling of warps. Also with our proposed approach, we observed that L1 cache load throughput increased by 2.75% for GEMM, 0.33% for 2DConv St and 0.46% for 2DConv Large respectively as data was resident in the L2 cache.

Memory management is a significant aspect of executing applications on GPUs even in the cloud environment. With the advancements in GPU architecture, issues such as data reuse, cache line eviction and data residency are to be considered when optimal performance for concurrently running applications. Frequency of data access from global memory has significant impact on the performance of the application with increased latencies when accesses result in cache misses. Through static profiling, we identify the access patterns to the global memory and investigate the relationship between frequent access patterns and data residency in the cache. From our investigations, we observed that each application frequently accesses a data region in memory though the range of addresses accessed differ. We evaluated our estimated set-aside area for LSTM and CSR applications. Executions using our proposed estimations shows a speed-up in the performance LSTM (1.004x) while CSR experienced a slow-down (0.998x) when both were co-executed with their respective estimated set-aside areas.

The diversity of workloads drives studies to use GPU more effectively to overcome the limited memory of GPUs. Precisely, it is essential to understand and utilize data locality of workloads to utilize the memory and cache efficiently, which is relatively smaller than CPU ' s. It is important to understand GPU memory hierarchy to efficiently use with multi-thread environment. Although there have been previous approaches to analyzing data locality on GPUs, these approaches focused on global memory and L2 cache levels with profiling at thread block levels. Data locality study in warp level in GPU has not been studied much. Especially, the concept of coalescing has been defined but the method of measuring the degree of coalescing has not been discussed. Our study focused on analyzing data locality in L1 cache levels, which is the smallest but fastest in cache level to analyze the impact of data locality. To achieve this analysis, our study profiles data locality in warp level, which is smallest segment in GPU thread groups. This paper introduces a novel perspective by introducing a quantitative measure for coalescing alongside static profiling of data locality. Furthermore, it offers a means of refining locality estimates by scrutinizing access patterns of L1 cache. To substantiate our approach, our study validates the estimated data locality against a range of real-world GPU benchmarks, including Rodina and Polybench. Through empirical experimentation, our results reveal a substantial correlation between the metrics of data locality and cache utilization, affirming the efficacy of our proposed method.

Recently, improving the overall resource utilization through efficient scheduling of applications on graphic processing unit (GPU) clusters has been a concern. Traditional cluster-orchestration platforms providing GPUs exclusively for applications constrain high resource utilization. Co-execution of GPU applications is suggested to utilize limited resources. However, the co-execution of GPU applications without considering their diverse characteristics can lead to their unpredictable performances owing to interference resulting from contention and unbalanced usage of resources among applications. This paper proposes an interference-aware execution framework with Co-scheML for various GPU applications such as high performance computing (HPC), deep learning (DL) training, and DL inference. Various resource-usage characteristics of GPU applications are analyzed and profiled to identify various degrees of their application interference. As interference prediction is challenging owing to the complexity of GPU systems, an interference model is generated by applying defined GPU metrics to machine learning (ML) models. A Co-scheML scheduler deploys applications to minimize the interference using the predicted interference from the constructed model. Experimental results of our framework demonstrated that the resource utilization improved by 24%, the average job completion time (JCT) improved by 23%, and the makespan shortened by 22% on average, compared to baseline schedulers.

Popular deep learning frameworks like PyTorch utilize GPUs heavily for training, and suffer from out-of-memory (OOM) problems if memory is not managed properly. CUDA Unified Memory (UM) allows the oversubscription of tensor objects in the GPU, but suffers from heavy performance penalties. In this paper, we build upon our UM implementation and create and utilize a minimal overhead CUPTI dynamic profiler to trace unified memory page fault and memory transfer statistics in PyTorch applications. We also implement CUDA memory prefetch and advise API which can be called directly from the PyTorch application based on the dynamically profiled statistics to improve oversubscription performance in various PyTorch models including Resnet and BERT.

The most scientific and numerical problems can be solved using the system of equations in linear algebra. Matrix-matrix multiplication is the foundation of linear algebra equations, and its optimization has an impact on the overall performance of a system. ScaLAPACK has established itself as the industry standard for dense linear algebraic computations, developed 30 years ago. Owing to advancements in microprocessor architectures, it is difficult to fully utilize the hardware capabilities of legacy software systems on modern architectures and achieve the maximum performance. In this study, we analyzed the effects of matrix size, register blocking parameters, and thread distribution on the performance, and improved our previously implemented matrix-matrix multiplication routine for matrix-panel multiplication, which performed well for large-sized square matrices. We also presented the ScaLAPACK QR factorization performance by replacing the double-precision general matrix-matrix multiplication routine (DGEMM) of ScaLAPACK with our matrix-matrix multiplication routine for a single node Intel Xeon Phi Knights Landing processor.

Data centers and cloud environments have recently started providing graphic processing unit (GPU)-based infrastructure services. Actual general purpose GPU (GPGPU) applications have low GPU utilization, unlike GPU-friendly applications. To improve the resource utilization of GPUs, there is the need for the concurrent execution of different applications while sharing resources in a streaming multiprocessor (SM). However, it is difficult to predict the execution performance of applications because resource contention can be caused by intra-SM multitasking. Furthermore, it is crucial to find the best resource partitioning and an execution set of applications that show the best performance among many applications. To address this, the current paper proposes K-Scheduler, a multitasking placement scheduler based on the intra-SM resource-use characteristics of applications. First, the resource-use and multitasking characteristics of applications are analyzed according to their classification and their individual execution characteristics. Rules for concurrent execution are derived according to each observation, and scheduling is performed according to the corresponding rules. The results verified that the total workload execution performance of K-Scheduler improved by 18% compared to previous studies, and individual execution performance improved by 32%.

Recently, graphic processing unit (GPU) multitasking has become important in many platforms since an efficient GPU multitasking mechanism can enable more GPU-enabled tasks running on limited physical GPUs. However, current GPU multitasking technologies, such as NVIDIA Multi-Process Service (MPS) and Hyper-Q may not fully utilize GPU resources since they do not consider the efficient use of intra-GPU resources. In this paper, we present smCompactor, which is a fine-grained GPU multitasking framework to fully exploit intra-GPU resources for different workloads. smCompactor dispatches any particular thread blocks (TBs) of different GPU kernels to appropriate stream multiprocessors (SMs) based on our profiled results of workloads. With smCompactor, GPU resource utilization can be improved as we can run more workloads on a single GPU while their performance is maintained. The evaluation results show that smCompactor improves resource utilization in terms of the number of active SMs by up to 33% and it reduces the kernel execution time by up to 26% compared with NVIDIA MPS.

본 연구는 A 사이버 대학의 한국어교육학 전공 편입생의 학업 목적과 학업에 대한 기대를 분석하여 교육과정 개선에 필요한 내용을 탐색하는 데 목적이 있다. 본 연구 목적 수행을 위해 3학년 편입생을 대상으로 설문조사를 실시하였다. 조사 결과, 한국어교원 자격증 취득이 학업 목적으로 나타났으며 자원봉사를 통한 한국어 교육에 대한 관심도 매우 높았다. 또한 학업 기간 내에 실무 지식과 현장 경험에 대한 학습 요구가 높았다. 이러한 연구 결과를 통해 앞으로 사이버대학의 한국어교육학 전공의 교육과정 구축 시, 학습자들의 학습 요구를 반영하여 자원봉사 한국어교육 현장 경험 확대와 학습자가 졸업 후 희망하는 실무 역량을 함양할 수 있는 다양한 비교과 프로그램이 활발히 운영되어야 할 것이다. 더불어 온라인 비교과 프로그램 수행 후 학습자들의 만족도 조사를 통한 환류 과정도 지속적으로 이루어져야 할 것이다.

Popular deep learning frameworks like PyTorch utilize GPUs heavily for training, and suffer from out-of-memory (OOM) problems if memory is not managed properly. In this paper, we propose a modification that utilizes CUDA Unified Memory (UM) to expand GPU memory to the available host memory space so that practicality for the programmer can increase, and OOM memory errors will not result for any workload. We also pinpoint performance issues that result from our modifications to the framework, and outline future plans like reducing redundant memory copies, prefetching, and memory advising techniques to improve upon our design. Our implementation shows that PyTorch UM performance overheads are minimal when the data footprint is below GPU memory capacity.

Recently, most cloud services use Docker container environment to provide their services. However, there are no researches to evaluate the performance of communication libraries for multi-GPU based distributed deep learning in a Docker container environment. In this paper, we propose an efficient communication architecture for multi-GPU based deep learning in a Docker container environment by evaluating the performances of various communication libraries. We compare the performances of the parameter server architecture and the All reduce architecture, which are typical distributed deep learning architectures. Further, we analyze the performances of two separate multi-GPU resource allocation policies - allocating a single GPU to each Docker container and allocating multiple GPUs to each Docker container. We also experiment with the scalability of collective communication by increasing the number of GPUs from one to four. Through experiments, we compare OpenMPI and MPICH, which are representative open source MPI libraries, and NCCL, which is NVIDIA's collective communication library for the multi-GPU setting. In the parameter server architecture, we show that using CUDA-aware OpenMPI with multi-GPU per Docker container environment reduces communication latency by up to 75%. Also, we show that using NCCL in All-reduce architecture reduces communication latency by up to 93% compared to other libraries.

계산 집약적인 응용을 가속화하기 위해 GPU(Graphics Processing Unit)가 널리 사용됨에 따라 데이터 센터 및 클라우드에서 GPU는 점점 더 많이 활용되고 있다. 여러 응용들의 동시 실행 요청이 있을 때 GPU 자원을 효율적으로 공유하도록 하는 연구는 아직 충분하지 않다. 또한, GPU 내의 자원을 효과적으로 공유하는 것은 응용의 자원 사용 패턴을 인지하지 않고서는 어렵다. 본 논문은 응용의 실행 패턴에 기반한 응용 분류법을 제시하고 자원 할당량 증가에도 성능이 향상되지 않는 이유를 런타임 특성에 따라 설명한다. 또한, 스레드 블록 기반 스케줄링 프레임워크인 smCompactor를 사용하여 분류된 응용을 기반으로 응용 조합의 동시 멀티태스킹 특성을 분석한다. 이를 통해 자원의 효율적인 활용이 가능한 응용의 조합을 파악한다. 응용 실행 특성을 고려하여 GPU상 멀티태스킹 실험을 진행한 결과, 기존 동시 실행 방법인 NVIDIA의 MPS와 비교하여 평균 28% 이상의 성능 향상을 보였다.