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Vasantha Erraguntla

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Proven technologist with over 25 years of experience in silicon design, research & development, innovation and technology management. Recognized industry leader with demonstrated abilities in turning research ideas into viable, scalable prototypes. Dynamic leader known for building strong organizations with innovative, inclusive and successful teams. Experienced in building strong, world-wide academic engagements. Recognized leader in technology and organizational leadership with significant technical publications and patents. Passionate and committed advocate for women in STEM.

Papers33 papers

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Session 10 overview: Mobile Systems-on-Chip (SoCs): Energy-efficient digital subcommittee

Erraguntla, Vasantha,Hashimoto, Takashi

Solid-State Circuits Conference Digest of Technical Papers, pp.174-175, (2014)

EIWOSBibtex

F3: Adaptive design techniques for energy efficiency

Eric Fluhr,Mike Polley,Sehyun Yang,Vasantha Erraguntla,Tobias G Noll,Kees Van Berkel

Solid-State Circuits Conference Digest of Technical Papers, pp.514-515, (2014)

EIWOSBibtex

Split-Path Fused Floating Point Multiply Accumulate (FPMAC)

Suresh Srinivasan,Ketan Bhudiya,Rajaraman Ramanarayanan,P. Sahit Babu,Tiju Jacob,Sanu K. Mathew,Ram Krishnamurthy,Vasantha Errgauntla

IEEE Symposium on Computer Arithmetic, pp.17-24, (2013)

Cited by1EIWOSBibtex

Split path multiply accumulate unit

Suresh Srinivasan,Rajaraman Ramanarayanan,Sanu Mathew,Ram Krishnamurthy,Vasantha Erraguntla

(2013)

Cited by1Bibtex

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Shailendra Jain,Surhud Khare,Satish Yada,V. Ambili,Praveen Salihundam,Shiva Ramani,Sriram Muthukumar,M. Srinivasan,Arun Kumar,Shasi Kumar,Rajaraman Ramanarayanan,Vasantha Erraguntla

ISSCC, pp.66-68, (2012)

Cited by273EIBibtex

An IA-32 processor with a wide voltage operating range in 32nm CMOS

Gregory Ruhl,Saurabh Dighe,Shailendra Jain,Surhud Khare,Satish Yada, V Ambili,Praveen Salihundam,Shiva Ramani,Sriram Muthukumar,Manali R Srinivasan,Arun Kumar,Shasi Kumar

ieee hot chips symposium, pp.1-37, (2012)

Bibtex

A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS

Praveen Salihundam,Shailendra Jain,Tiju Jacob,Shasi Kumar,Vasantha Erraguntla,Yatin Hoskote,Sriram R. Vangal,Gregory Ruhl,Nitin Borkar

IEEE Journal of Solid-state Circuits, no. 4 (2011): 757-766

Cited by105EIBibtex

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Rajaraman Ramanarayanan,Sanu Mathew,Farhana Sheikh,Suresh Srinivasan,Amit Agarwal,Steven Hsu,Himanshu Kaul,Mark A Anders,Vasantha Erraguntla,Ram Krishnamurthy

Seville, pp.210-213, (2010)

Cited by2EIWOSBibtex

A 2Tb/s 6×4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS

Praveen Salihundam,Shailendra Jain,Tiju Jacob,Shasi Kumar,Vasantha Erraguntla,Yatin Hoskote,Sriram R Vangal,G Ruhl,Partha Kundu,Nitin Borkar

VLSI Circuits, pp.79-80, (2010)

Cited by15EIWOSBibtex

Session 18 overview: Power efficient media processing

Southerland, Raney,Erraguntla, Vasantha

Solid-State Circuits Conference Digest of Technical Papers, (2010)

EIWOSBibtex

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

Saurabh Dighe,Sriram R. Vangal,Paolo A. Aseron,Shasi Kumar,Tiju Jacob,Keith A. Bowman,Jason Howard,James Tschanz,Vasantha Erraguntla,Nitin Borkar,Vivek De,Shekhar Borkar

ISSCC, pp.174-175, (2010)

Cited by67EIBibtex

2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS

Suresh Srinivasan,Sanu Mathew,Rajaraman Ramanarayanan,Farhana Sheikh,Mark A Anders,Himanshu Kaul,Vasantha Erraguntla,Ram Krishnamurthy,Greg Taylor

VLSI Circuits, pp.203-204, (2010)

Cited by18EIWOSBibtex

A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS

Suresh Srinivasan,Sanu Mathew,Vasantha Erraguntla,Ram Krishnamurthy

VLSI Design, pp.301-306, (2009)

Cited by18EIWOSBibtex

Combined set bit count and detector logic

Rajaraman Ramanarayanan,Sanu Mathew,Ram Krishnamurthy,Shay Gueron,Vasantha Erraguntla

(2008)

Cited by1Bibtex

A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores

Rajaraman Ramanarayanan,Sanu Mathew,Vasantha Erraguntla,Ram Krishnamurthy,Shay Gueron

VLSI Design, pp.273-278, (2008)

Cited by1EIBibtex

Hardware-based multi-threading for packet processing

Yatin Hoskote,Sriram R Vangal,Vasantha Erraguntla,Nitin Borkar

(2005)

Cited by24Bibtex

METHOD AND SYSTEM TO DETERMINE A CLOCK SIGNAL FOR PACKET PROCESSING

Sriram R Vangal,Yatin Hoskote,Nitin Borkar, X U Jianping,Vasantha Erraguntla,Shekhar Borkar

(2005)

Bibtex

5 Chapter - A high-speed, multithreaded TCP offload engine for 10 Gb/s ethernet

Yatin Hoskote,Sriram R Vangal,Vasantha Erraguntla,Nitin Borkar

(2005)

Bibtex

Network protocol processor

Sriram R Vangal,Yatin Hoskote,Vasantha Erraguntla,Nitin Borkar

(2005)

Bibtex

Network protocol off-load engines

Sriram R Vangal,Yatin Hoskote,Vasantha Erraguntla, Jianping Xu

(2004)

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