For contributions to the study of graph-theoretic models of computation, emphasizing theoretical studies of parallel algorithms and architectures, VLSI design and layout, and data structures.
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On January 1, 2008, I retired from the University of Massachusetts Amherst, where I held the rank of Distinguished University Professor in Computer Science. I now spend most of my time doing research and writing, with an appointment as Research Professor of Computer Science at Northeastern University (Boston, MA). I had an appointment as Research Professor of ECE [primary] and Computer Science [secondary] at Colorado State University from 2008-2012. Before I joined UMass in 1986, I was a Professor of Computer Science at Duke University from 1981 to 1986, and a Research Staff Member at the IBM Watson Research Center from 1965 to 1981. Over the years, I held visiting positions at Yale University and the University of Toronto, in addition to part-time positions at the predecessor of Polytechnic University and at New York University. I was a Lady Davis Visiting Professor at the Technion (Israel Institute of Technology) and a Fulbright Senior Research Scholar at the University of Paris-South. My research program is continuing unabated post-retirement---perhaps even at a higher level of intensity, with no required teaching and committee work. My main research focus is on developing algorithmic models and techniques to deal with the many new modalities of "collaborative computing," the use of many, possibly geographically dispersed, computers to cooperatively solve individual computing problems. My current main research/writing projects include: AREA-oriented scheduling and IC-scheduling: This is my main research focus. The project is devoted to a new paradigm for scheduling complex computations (modeled as DAGs) for modern task-hungry, dynamically heterogeneous computing platforms, including many modalities of Internet-based computing such as cloud computing, grid computing, volunteer computing, desktop-grid computing), aggressively multicore architectures, and proposed exascale architectures.