Bangan Liu - Tokyo Institute of Technology

基本信息

Career Trajectory

Bio

Bangan Liu currently works at the Department of Physical Electronics, Tokyo Institute of Technology. Bangan does research in Electrical Engineering. Their most recent publication is 'A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique'.

Research Interests

Papers共 63 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

A Fully Synthesizable Fractional-N MDLL with Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range

Hongye Huang,Bangan Liu,Zezheng Liu,Dingxin Xu,Yuncheng Zhang,Waleed Madany,Junjun Qiu,Zheng Sun,Ashbir Aviat Fadila,Jian Pang,Zheng Li,Dongwon You,Atsushi Shirane,Kenichi Okada

IEEE solid-state circuits letters（2024）

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10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter

Dingxin Xu,Zezheng Liu, Yifeng Kuai,Hongye Huang,Yuncheng Zhang,Zheng Sun,Bangan Liu,Wenqian Wang,Yuang Xiong,Junjun Qiu,Waleed Madany,Yi Zhang,Ashbir Aviat Fadila,Atsushi Shirane,Kenichi Okada

IEEE International Solid-State Circuits Conference（2024）

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A 6.5-to-8-ghz Cascaded Dual-Fractional- $N$ Digital PLL Achieving $-$ 52.79-Dbc Fractional Spur with 50-Mhz Reference

Dingxin Xu,Yuncheng Zhang,Hongye Huang,Zheng Sun,Bangan Liu,Ashbir Aviat Fadila,Junjun Qiu,Zezheng Liu,Wenqian Wang, Yuang Xiong, Waleed Madany,Atsushi Shirane,Kenichi Okada

IEEE Journal of Solid-State Circuitsno. 99 (2024): 1-13

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A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-Bit Delta-Sigma Modulator and Transformer Combined FIR FIlter

Yuncheng Zhang,Zheng Sun,Bangan Liu,Junjun Qiu,Dingxin Xu,Yi Zhang,Xi Fu,Dongwon You,Hongye Huang,Waleed Madany,Ashbir Aviat Fadila,Zezheng Liu,Wenqian Wang,Yuang Xiong,Atsushi Shirane,Kenichi Okada

IEEE journal of solid-state circuitspp.1-13, (2024)

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A 6.5-to-8ghz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7Dbc Fractional Spurs with 50mhz Reference

Dingxin Xu,Yuncheng Zhang,Hongye Huang,Zheng Sun,Bangan Liu,Ashbir Aviat Fadila,Junjun Qiu,Zezheng Liu,Wenqian Wang,Yuang Xiong,Waleed Madany,Atsushi Shirane,Kenichi Okada

CICCpp.1-2, (2023)

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A 32Khz-Reference 2.4ghz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration

Junjun Qiu,Wenqian Wang,Zheng Sun,Bangan Liu,Yuncheng Zhang,Dingxin Xu,Hongye Huang,Ashbir Aviat Fadila,Zezheng Liu,Waleed Madany,Yuang Xiong,Atsushi Shirane,Kenichi Okada

ISSCCpp.80-81, (2023)

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A 1-Bit-DSM-Based Digital Polar Power Amplifier Supporting 1024-QAM

Yuncheng Zhang,Bangan Liu,Junjun Qiu,Atsushi Shirane,Kenichi Okada

IEEE Solid-State Circuits Letters（2022）

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A 0.37mm² Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components

Yuncheng Zhang,Bangan Liu,Teruki Someya,Rui Wu,Junjun Qiu,Atsushi Shirane,Kenichi Okada

IEICE Transactions on Electronicsno. 7 (2022): 334-342

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A CMOS 24-30-GHz Low-Phase-Variation Variable Gain Amplifier Design for 5G New Radio

Junjun Qiu,Jian Pang,Bangan Liu,Xueting Luo,Yun Wang,Yuncheng Zhang,Atsushi Shirane,Kenichi Okada

IEEE Solid-State Circuits Letters（2022）

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A Low-Power Digital Baseband Circuit for GMSK Demodulation in Sub-Ghz Application

Junjun Qiu,Bangan Liu,Yuncheng Zhang,Atsushi Shirane,Kenichi Okada

IEICE electronics express（2022）

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