Home Research-feed Channel Rankings GCT THU AI TR Open Data Must Reading

views: 3

Chieh-Fang Chen

Sign in to view more

Show Academic Trajectory

Ego Network

D-Core

Research Interests

Author Statistics

Experience

Education

Bio

None

Papers6 papers

Sort

By YearBy Citation

A 128Gb (MLC)/192Gb (TLC) single-gate vertical channel (SGVC) architecture 3D NAND using only 16 layers with robust read disturb, long-retention and excellent scaling capability

Hang-Ting Lue,Pei-Ying Du,Wei-Chen Chen, Yung-Chun Lee,Tzu-Hsuan Hsu,Teng-Hao Yeh,Kuo-Pin Chang,Chih-Chang Hsieh, Chiatze Huang, Guan-Ru Lee,Chih-Ping Chen,Chieh-Fang Chen

international electron devices meeting, (2017)

Bibtex

A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity

Hang-Ting Lue,Tzu-Hsuan Hsu,Chen-Jun Wu,Wei-Chen Chen,Teng-Hao Yeh,Kuo-Pin Chang,Chih-Chang Hsieh,Pei-Ying Du,Yi-Hsuan Hsiao, Yu-Wei Jiang, Guan-Ru Lee,Roger Lo

international electron devices meeting, (2015): 44-47

Bibtex

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

Shihhung Chen, H Y Lue,Yenhao Shih,Chiehfang Chen,Tzuhsuan Hsu,Yanru Chen,Yihsuan Hsiao, Shihcheng Huang,Kuopin Chang,Chihchang Hsieh, Guanru Lee, Alfredtunghua Chuang

Electron Devices Meeting, pp.2.3.1-2.3.4, (2012)

Cited by23EIWOSBibtex

Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash

Chunhsiung Hung,Hangting Lue, Shuonan Hung,Chihchang Hsieh,Kuopin Chang, Shihlin Huang, Tzung Shen Chen,Chihshen Chang, Wenwei Yeh,Yihsuan Hsiao,Chiehfang Chen,Yanru Chen

(2012)

Cited by9Bibtex

The Influence of Nitrogen Doping on the Chemical and Local Bonding Environment of Amorphous and Crystalline Ge 2 Sb 2 Te 5

Joseph Washington,Eric A Joseph,M A Paesler,G Lucovsky,J L Jordansweet,Simone Raoux,Chiehfang Chen,A Pyzyna,R Dasaka,Chung H Lam,Alejandro G Schrott,J C Woicik

(2009)

Cited by1Bibtex

High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply

Yuan Taur,S J Wind,Y J Mii,Y T Lii, Dan Moy,K A Jenkins,C L Chen,P J Coane,D Klaus, J J Bucchignano,M G Rosenfield, M G R Thomson

Washington, DC, USA, pp.127-130, (1993)

Cited by167EIWOSBibtex

View All

Base Info Papers Patents Projects