D. Mahaveer Sathaiya - TCAD, Taiwan Semiconductor Manufacturing Company

基本信息

Career Trajectory

Bio

D. Mahaveer Sathaiya received the B.E. degree in electronics and communication engineering from M. V. Jayaraman College of Engineering, Bangalore, India, in 1999, and the M.S. degree in electrical engineering, in 2003, from the Indian Institute of Technology Madras (IITM), Chennai, India, where he is working toward the Ph.D. degree. He is currently a Principal Engineer in Technology Computer-Aided Design (TCAD) Division, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan. He is also with the Department of Electrical Engineering, IITM. His current research interests include device/process modeling and simulation.

Research Interests

Papers共 12 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

A Novel Method to Extract Channel Mobility and Parasitic Resistance of 2-D Material MOSFETs

Aslan Wei,D. Mahaveer Sathaiya,Terry Y. T. Hung,Edward Chen, Tai-Yuan Wang, Wen-Chia Wu,Chao-Ching Cheng,Iuliana P. Radu,Jeff Wu,Chung-Cheng Wu

IEEE TRANSACTIONS ON ELECTRON DEVICESno. 10 (2024): 6424-6429

Cited0Views0EIWOSBibtex

On the Extreme Scaling of Transistors with Monolayer MOS2 Channel

Wen-Chia Wu,Terry Y. T. Hung,D. Mahaveer Sathaiya,Edward Chen,Chen-Feng Hsu, Walker Yun,Hsiang-Chi Hu,Bo-Heng Liu,T. Y. Lee,Chi-Chung Kei,Wen-Hao Chang,Jin Cai, W. Jeff,Chung-Cheng Wu,H.-S. Philip Wong,Chao-Hsin Chien,Chao-Ching Cheng,Iuliana P. Radu

Symposium on VLSI Technologypp.1-2, (2024)

Cited0Views0EIWOSBibtex

Building High Performance Transistors on Carbon Nanotube Channel

VLSI Technology and Circuitspp.1-2, (2023)

Cited5Views0EIWOSBibtex

Monolayer-MoS2 Stacked Nanosheet Channel with C-type Metal Contact

2023 International Electron Devices Meeting (IEDM)pp.1-4, (2023)

Cited0Views0EIWOSBibtex

Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel

2023 International Electron Devices Meeting (IEDM)pp.1-4, (2023)

Cited0Views0EIWOSBibtex

Scaled Contact Length with Low Contact Resistance in Monolayer 2D Channel Transistors

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (2023)

Cited4Views0EIWOSBibtex

Comprehensive Study of Contact Length Scaling Down to 12 Nm with Monolayer MoS2 Channel Transistors

IEEE TRANSACTIONS ON ELECTRON DEVICESno. 12 (2023): 6680-6686

Cited1Views0EIWOSBibtex

Comprehensive Physics Based TCAD Model for 2D MX2 Channel Transistors

D. Mahaveer Sathaiya,Terry Y. T. Hung,Edward Chen,Wen-Chia Wu,Aslan Wei,Chih-Piao Chuu,Sheng-Kai Su,Ang Sheng Chou,Cheng-Ting Chung,Chao-Hsin Chien,Han Wang,Jin Cai,Chung-Cheng Wu,Iuliana P. Radu,Jeff Wu

2022 International Electron Devices Meeting (IEDM) (2022)

Cited1Views0EIWOSBibtex

A Closed-Form Model for Thermionic Trap-Assisted Tunneling

D. Mahaveer Sathaiya,Shreepad Karmalkar

IEEE Transactions on Electron Devices（2008）

Cited20Views0EIWOSBibtex

Edge Effects on Gate Tunneling Current in Hemts

D. Mahaveer Sathaiya,Shreepad Karmalkar

IEEE transactions on electron devices/IEEE transactions on electron devices（2007）

Cited47Views0EIWOSBibtex

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