Prior to joining Galois, Dr. Archer led the Deep Sub-micron CAE business unit at Mentor Graphics, directed engineering on workstation and server chipsets at Intel, was instrumental in development of the communication architecture of the ASCI Red TeraFLOPS system developed by Intel Supercomputer Division, and participated in the design of multiple generations of custom CPU products. Dr. Archer holds a Ph.D. in Computer Science from Portland State University as well as an M.S. in Electrical Engineering from the University of Illinois at Urbana-Champaign. Patents US Patent 6,148,356,“Scalable Computer System” US Patent 6,021,457,“Method/Apparatus for Minimizing Perturbation While Monitoring Parallel Applications” US Patent 5,634,043,“Microprocessor Point-to-Point Communication” US Patent 5,317,720, “Processor System with Write-back Cache Using Write-back and non Write-back Transactions Stored in Separate Queues” Recent Invited Talks Archer, D. Performance Optimization of Linear Secret Sharing MPC for Real Applications. European Workshop on the Theory and Practice of Multiparty Computation, 2014. Archer, D., Butler, K., Nazario, J., Rosulek, M., Traynor, P. Toward Quantitative Metrics in the MPC Security-Influence-Performance Continuum. IARPA SPAR-MPC Workshop, 2014. Archer, D. Toward Making Secure Computation Practical. 2014 Computer Security Day, University of Oregon, 2014