Edmund J. Sprogis

IBM Systems and Technology Group, Essex Junction, Vermont

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Papers9 papers

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Three-dimensional silicon integration

J. U. Knickerbocker,P. S. Andry,B. Dang,R. R. Horton,M. J. Interrante,C. S. Patel,R. J. Polastre,K. Sakuma, R. Sirdeshmukh,E. J. Sprogis,S. M. Sri-Jayantha, A. M. Stephens

IBM Journal of Research and Development, no. 6 (2008): 553-569

Cited by147EIBibtex

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

K. Sakuma,P. S. Andry,C. K. Tsang,S. L. Wright,B. Dang,C. S. Patel,B. C. Webb,J. Maria,E. J. Sprogis,S. K. Kang,R. J. Polastre,R. R. Horton

IBM Journal of Research and Development, no. 6 (2008): 611-622

Cited by107EIBibtex

3D chip stacking with C4 technology

B. Dang,S. L. Wright,P. S. Andry,E. J. Sprogis,C. K. Tsang,M. J. Interrante,B. C. Webb,R. J. Polastre,R. R. Horton,C. S. Patel,A. Sharma,J. Zheng

IBM Journal of Research and Development, no. 6 (2008): 599-609

Cited by35EIBibtex

Wafer-level 3D integration technology

S. J. Koester,A. M. Young,R. R. Yu, S. Purushothaman, K.-N. Chen,D. C. La Tulipe,N. Rana,L. Shi,M. R. Wordeman,E. J. Sprogis

IBM Journal of Research and Development, no. 6 (2008): 583-597

Cited by158EIBibtex

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

P. S. Andry,C. K. Tsang,B. C. Webb,E. J. Sprogis,S. L. Wright,B. Dang,D. G. Manzer

IBM Journal of Research and Development, no. 6 (2008): 571-581

Cited by78EIBibtex

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

John U Knickerbocker,Chirag S Patel,Paul S Andry,Cornelia K Tsang,L. P. Buchwalter,Edmund J Sprogis,Hua Gan,R. R. Horton,R. J. Polastre,S. L. Wright,John M Cotte

IEEE Journal of Solid-State Circuits, no. 8 (2006): 1718-1725

Cited by101EIWOSBibtex

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

J. U. Knickerbocker,P. S. Andry,L. P. Buchwalter,A. Deutsch,R. R. Horton,K. A. Jenkins,Y. H. Kwark,G. McVicker,C. S. Patel,R. J. Polastre,C. Schuster,A. Sharma

IBM Journal of Research and Development, no. 4/5 (2005): 725-753

Cited by268EIBibtex

A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's

N. C. Lu,P. E. Cottrell, W. J. Craig,S. Dash,D. L. Critchlow,R. L. Mohler,B. J. Machesney,T. H. Ning,W. p. No,R. M. Parent,R. E. Scheuerlein,E. J. Sprogis

IEEE Journal of Solid-state Circuits, no. 5 (1986): 627-634

Cited by13Bibtex

system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

J. U. Knickerbocker,P. S. Andry,L. P. Buchwalter,A. Deutsch,R. R. Horton,K. A. Jenkins,Y. H. Kwark,G. McVicker,C. S. Patel,R. J. Polastre,C. Schuster,A. Sharma

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Edmund J. SprogisBinding

Papers9 papers

Edmund J. Sprogis