基本信息
浏览量:3
职业迁徙
个人简介
Jaesik Lee received the B.E. and M.E. degrees in material sciences and engineering from University of Seoul, Seoul, Korea, and the Ph.D. degree in advanced microelectronics packaging process development from the University of Waterloo, Waterloo, ON, Canada, in 2008.
He is currently a Principal Engineer with GlobalFoundries, Dresden, Germany, working on 28 nm consumer price index (CPI) and 3-D through silicon via (TSV) technology development. He joined System LSI, Samsung Electronics Company Ltd., Seoul, Korea, from 2008 to 2010, where he worked on 32 nm complementary metal-oxide semiconductor (CMOS) node CPI, and 130 $\mu{\rm m}$ pitch Cu-pillar flipchip process and material. He moved to the Institute of Microelectronics, Singapore, in 2010, working on 3-D TSV integration and ultra-fine pitch flipchip technology development using Cu-pillars. His current research interests include 3-D integrated circuit integration with TSV and CPI technology development on advanced CMOS nodes with ELK.
研究兴趣
论文共 7 篇作者统计合作学者相似作者
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引用量
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期刊级别
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合作机构
IEEE transactions on components, packaging, and manufacturing technologyno. 6 (2012): 964-970
Components, Packaging and Manufacturing Technology, IEEE Transactionsno. 12 (2011): 1988-1995
作者统计
#Papers: 7
#Citation: 64
H-Index: 4
G-Index: 4
Sociability: 3
Diversity: 1
Activity: 0
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