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个人简介
Jaewon Park received the B.S. degree from the University of Suwon, Hwaseong, South Korea, in 2009, and the Ph.D. degree from Yonsei University, Seoul, South Korea, in 2021.
In 2014, he joined the Memory Division, Samsung Electronics, Hwaseong, where he has been involved in low-power DRAM circuit design. He has been involved in high-bandwidth memory (HBM) chip design since 2016. His research interests include 3-D-DRAM circuit design and technology, and design for testibility (DFT), including memory built-in self-test (MBIST) in DRAM design.
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Yesin Ryu,Sung-Gi Ahn,Jae Hoon Lee,Jaewon Park,Yong Ki Kim, Hyochang Kim, Yeong Geol Song,Han-Won Cho, Sunghye Cho,Seung Ho Song,Haesuk Lee,Useung Shin,
IEEE Journal of Solid-State Circuitsno. 4 (2023): 1051-1061
Yesin Ryu,Young-Cheon Kwon,Jae Hoon Lee,Sung-Gi Ahn,Jaewon Park,Kijun Lee, Yu Ho Choi,Han-Won Cho, Jae San Kim,Jungyu Lee,Haesuk Lee,Seung Ho Song,
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D-Core
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