Kamakoti Veezhinathan

Department of Computer Science and Engineering, IIT Madras

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Papers15 papers

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Brutus : Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER

Rahul Bodduna, Vinod Ganesan, Patanjali SLPSK,Kamakoti Veezhinathan,Chester Rebeiro

IEEE Computer Architecture Letters, no. 1 (2020): 9-12

EIWOSBibtex

A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks

Arnab Roy,Swagath Venkataramani,Neel Gala, Sanchari Sen,Kamakoti Veezhinathan,Anand Raghunathan

ISLPED, pp.1-6, (2017)

Cited by4EIBibtex

Shakti-T: A RISC-V Processor with Light Weight Security Extensions

Arjun Menon, Subadra Murugan,Chester Rebeiro,Neel Gala,Kamakoti Veezhinathan

HASP@ISCA, (2017)

Cited by22EIBibtex

Component fault localization using switching current measurements

Seetal Potluri,Satya Trinadh, Siddhant Saraf,Kamakoti Veezhinathan

ETS, pp.1-2, (2016)

EIBibtex

Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures

Sanjay Burman,Seetal Potluri,Debdeep Mukhopadhyay,Kamakoti Veezhinathan

J. Low Power Electronics, no. 2 (2016): 99-106

EIBibtex

Utilizing Faulty Cores

Karthik Raghavan,Kamakoti Veezhinathan

IETE Technical Review, no. 5 (2014)

Cited by1Bibtex

Network-on-Chips on 3-D ICs: Past, Present, and Future

M Pawan Kumar,Srinivasan Murali,Kamakoti Veezhinathan

IETE Technical Review, no. 4 (2014)

Cited by9Bibtex

A syllable based statistical text to speech system

Abhijit Pradhan,Aswin Shanmugam S,Anusha Prakash,Kamakoti Veezhinathan,Hema Murthy

EUSIPCO, pp.1-5, (2013)

Cited by6EIBibtex

Network-on-chips on 3-D ICs: Past, present, and future

Kamakoti Veezhinathan,Srinivasan Murali, Mpawan Kumar

Iete Technical Review, (2012)

Cited by3Bibtex

The implications of shared data synchronization techniques on multi-core energy efficiency

Ashok Gautham,Kunal Korgaonkar,Patanjali Slpsk,Shankar Balachandran,Kamakoti Veezhinathan

HotPower, pp.6-6, (2012)

Cited by29EIBibtex

Utilizing Faulty Cores

Kamakoti Veezhinathan, Karthik Raghavan

Iete Technical Review, (2011)

Cited by1Bibtex

A Method for Integrating Network-on-Chip Topologies with 3D ICs

M. Pawan Kumar,Anish S. Kumar,Srinivasan Murali,Luca Benini,Kamakoti Veezhinathan

ISVLSI, pp.60-65, (2011)

Cited by5EIBibtex

LFSR based stream ciphers are vulnerable to power attacks

Sanjay Burman,Debdeep Mukhopadhyay,Kamakoti Veezhinathan

INDOCRYPT, pp.384-392, (2007)

Cited by41EIBibtex

An Optimal Algorithm for Computing Vissible Nearest Foreign Neighbors Among Colored Line Segments

Thorsten Graf,Kamakoti Veezhinathan

SWAT, (1998): 59-70

Cited by1EIBibtex

Reducing Simple Polygons to Triangles - A Proof for an Improved Conjecture

Thorsten Graf,Kamakoti Veezhinathan

ICALP, (1998): 130-139

Cited by2EIBibtex

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Kamakoti VeezhinathanBinding

Papers15 papers

Kamakoti Veezhinathan