Memory System Architecture Team at AMD
Current: Memory System, Interconnect, Coherence Protocol, and general System Architect for next-generation design at AMD. Previous: 2012-2014: Samsung Austin Research Center (SARC): Principal System Performance Architect for clean-sheet ARM ISA custom on-chip interconnect, DRAM controller, and CPU last level cache for IP designs targeting multiple market segments. Management and oversight for a small (5-8) team of performance analysts and modeling engineers. Work with RTL /Design teams on definition (considering performance, functional correctness, etc) of above items including Mobile Memory System QoS. Sidelines in core uArch and Power Management algorithms, modeling, and design for Mobile. 2009-2012: System Architect for future AMD Opteron-family processor and future platform. Primary technical liason between program Chief Engineer and technical teams spanning SOC, microarchitecture, platform architecture, performance evaluation, etc disciplines exploring multiple technical aspects and coordination of design. 2003-2009: Computer architecture/system performance modeling and architecture. Special emphasis on multiprocessors (CMP, SMP) and memory systems (last level cache, DRAM, coherent interconnect/coherence protocols, etc.) Additional experience in processor core microarchitecture and performance, including various aspects of power management. Goals: Improve computer system performance through high performance design of above. Specialties: Server architecture, memory system design/performance.