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Dr. Chen leads an analog mixed-signal circuit group, working on various circuit and system design problems for wireless, wireline, biomedical and processor applications. Some examples include high-speed low-power data converters, clock generation, RF power amplifier, and bio-inspired computing circuits. He and his students enjoy exploring circuit architectural opportunities that excel beyond the technology limitation. With this passion, his research group has fortunately demonstrated several record-setting performances in PA, ADC, DAC, and PLL to date via architecture innovations. As a graduate student researcher, he also proposed and demonstrated the asynchronous SAR ADC architecture, which has been adopted today for low-power high-speed analog-to-digital conversion products in industry. From 2006 to 2010, he has been a member of Analog IC Group at Atheros Communications (now Qualcomm), working on mixed-signal and RF circuits for various wireless communication products.
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Wenhao Song,Mingyi Rao,Yunning Li,Can Li,Ye Zhuo,Fuxi Cai, Mingche Wu, Wenbo Yin, Zongze Li, Qiang Wei, Sangsoo Lee, Hengfang Zhu,
Science (New York, N.Y.)no. 6685 (2024): 903-910
IEEE JOURNAL OF SOLID-STATE CIRCUITSno. 1 (2024): 40-51
2023 IEEE International Solid-State Circuits Conference (ISSCC)pp.226-228, (2023)
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2023 IEEE Custom Integrated Circuits Conference (CICC)pp.1-2, (2023)
IEEE Journal of Solid-State Circuitsno. 5 (2023): 1201-1211
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) (2022): 526-531
2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)pp.3-6, (2022)
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