Robert J. Polastre

IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York

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Papers21 papers

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Integration and Packaging of Embedded Radial Micro-Channels for 3D Chip Cooling

Bing Dang,Evan G. Colgan, Fanghao Yang, Mark D. Schultz, Yang Liu,Qianwen Chen,Jae-Woong Nah,Robert J. Polastre,Michael A. Gaynes,Gerard McVicker,Pritish R. Parida,Cornelia K. Tsang

Electronic Components and Technology Conference, pp.1271-1277, (2016)

Bibtex

Embedded Two-Phase Cooling of Large Three-Dimensional Compatible Chips With Radial Channels

Mark D. Schultz, Fanghao Yang,Evan G. Colgan,Robert J. Polastre,Bing Dang,Cornelia K. Tsang,Michael A. Gaynes,Pritish R. Parida,John U. Knickerbocker,Timothy J. Chainer

JOURNAL OF ELECTRONIC PACKAGING, no. 2 (2016): 021005

Bibtex

Measurement of microbump thermal resistance in 3D chip stacks

Evan G Colgan,Paul S Andry,Bing Dang,J H Magerlein,Joana Maria,R J Polastre,Jamil Wakil

Semiconductor Thermal Measurement and Management Symposium, pp.1-7, (2012)

EIWOSBibtex

2.5D and 3D technology challenges and test vehicle demonstrations

John U Knickerbocker,Paul S Andry,Evan G Colgan,Bing Dang,Timothy O Dickson,X Gu,Chuck Haymes,Christopher V Jahnes,Y Liu,J P Maria,R J Polastre,Cornelia K Tsang

Electronic Components and Technology Conference, pp.1068-1076, (2012)

Cited by87EIWOSBibtex

Silicon Microchannel Cooling for High Power Chips

Evan G Colgan,Bruce K Furman, Michael A Gaynes,Nancy C Labianca,J H Magerlein,R J Polastre,Raschid J Bezama, R K Choudhary, Kenneth C Marston,Hilton T Toy,Jamil Wakil,Roger R Schmidt

Hvac&r Research, (2011)

Cited by1Bibtex

High Conductivity Gate Metallurgy for Tft/Lcd's

Peter M Fryer,Evan G Colgan,E Galligan,W Graham,Radley M Horton,Leslie Charles Jenkins,R John,Yuanjui Kuo,K Latzko,Frank R Libsch, Alan Lien,R Nywening

(2011)

Cited by1Bibtex

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

K. Sakuma,P. S. Andry,C. K. Tsang,S. L. Wright,B. Dang,C. S. Patel,B. C. Webb,J. Maria,E. J. Sprogis,S. K. Kang,R. J. Polastre,R. R. Horton

IBM Journal of Research and Development, no. 6 (2008): 611-622

Cited by107EIBibtex

3D chip stacking with C4 technology

B. Dang,S. L. Wright,P. S. Andry,E. J. Sprogis,C. K. Tsang,M. J. Interrante,B. C. Webb,R. J. Polastre,R. R. Horton,C. S. Patel,A. Sharma,J. Zheng

IBM Journal of Research and Development, no. 6 (2008): 599-609

Cited by35EIBibtex

Three-dimensional silicon integration

J. U. Knickerbocker,P. S. Andry,B. Dang,R. R. Horton,M. J. Interrante,C. S. Patel,R. J. Polastre,K. Sakuma, R. Sirdeshmukh,E. J. Sprogis,S. M. Sri-Jayantha, A. M. Stephens

IBM Journal of Research and Development, no. 6 (2008): 553-569

Cited by147EIBibtex

High Performance and Subambient Silicon Microchannel Cooling

E. G. Colgan, B. Furman,M. Gaynes,N. LaBianca,J. H. Magerlein,R. Polastre,R. Bezama,K. Marston,R. Schmidt

JOURNAL OF HEAT TRANSFER-TRANSACTIONS OF THE ASME, no. 8 (2007): 1046-1051

Cited by29Bibtex

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

Evan G Colgan,Bruce K Furman,A Gaynes,W Graham,Nancy C Labianca,J H Magerlein,R J Polastre,Mary Beth Rothwell,Raschid J Bezama,R K Choudhary,Kenneth C Marston, Hilton T Toy

IEEE Transactions on Components and Packaging Technologies, no. 2 (2007): 218-225

Cited by107EIWOSBibtex

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

John U Knickerbocker,Chirag S Patel,Paul S Andry,Cornelia K Tsang,L. P. Buchwalter,Edmund J Sprogis,Hua Gan,R. R. Horton,R. J. Polastre,S. L. Wright,John M Cotte

IEEE Journal of Solid-State Circuits, no. 8 (2006): 1718-1725

Cited by101EIWOSBibtex

3-D silicon integration and silicon packaging technology using silicon through-vias

John U. Knickerbocker,Chirag S. Patel,Paul S. Andry,Cornelia K. Tsang,L. Paivikki Buchwalter,Edmund J. Sprogis, Hua Gan,Raymond R. Horton,Robert J. Polastre,Steven L. Wright,John M. Cotte

custom integrated circuits conference, no. 8 (2006): 1718-1725

Bibtex

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

J. U. Knickerbocker,P. S. Andry,L. P. Buchwalter,A. Deutsch,R. R. Horton,K. A. Jenkins,Y. H. Kwark,G. McVicker,C. S. Patel,R. J. Polastre,C. Schuster,A. Sharma

IBM Journal of Research and Development, no. 4/5 (2005): 725-753

Cited by268EIBibtex

Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology

John U. Knickerbocker,Chirag S. Patel,Paul S. Andry,Cornelia K. Tsang,L. Paivikki Buchwalter,Edmund J. Sprogis,Hua Gan,Raymond R. Horton,Robert J. Polastre,Steven L. Wright,Christian D. Schuster,Christian W. Baks

IEEE Custom Integrated Circuits Conference, pp.659-662, (2005)

Cited by28EIWOSBibtex

Electrical Test Sites for AMLCD-TFT Array Process Characterization

Evan G Colgan,R J Polastre,Masatomo Takeichi,Robert L Wisnieff

(1998)

Bibtex

A 10.5-in.-diagonal SXGA active-matrix display

E. G. Colgan,P. M. Alt,R. L. Wisnieff,P. M. Fryer,E. A. Galligan,W. S. Graham,P. F. Greier,R. R. Horton,H. Ifill,L. C. Jenkins,R. A. John,R. I. Kaufman

IBM Journal of Research and Development, no. 3-4 (1998): 427-444

Cited by21EIBibtex

Thin-film-transistor process-characterization test structures

E. G. Colgan,R. J. Polastre,Takeichi, M.,R. L. Wisnieff

IBM Journal of Research and Development, no. 3-4 (1998): 481-490

Cited by6EIWOSBibtex

A six-mask TFT-LCD process using copper-gate metallurgy

P. M. Fryer,E. Colgan,E. Galligan,W. Graham,R. Horton,D. Hunt,L. Jenkins,R. John,P. Koke,Y. Kuo,K. Latzko,F. Libsch

Journal of The Society for Information Display, no. 1 (1997)

Cited by12Bibtex

system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

J. U. Knickerbocker,P. S. Andry,L. P. Buchwalter,A. Deutsch,R. R. Horton,K. A. Jenkins,Y. H. Kwark,G. McVicker,C. S. Patel,R. J. Polastre,C. Schuster,A. Sharma

Bibtex

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Robert J. PolastreBinding

Papers21 papers

Robert J. Polastre