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Lo, R.

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Study of Thyristor-Mode Dual-Channel NAND Flash Devices

Roger Lo,Hang-Ting Lue,Wei-Chen Chen,Pei-Ying Du,Tzu-Hsuan Hsu,Tuo-Hung Hou, Keh-Chung Wang,Chih-Yuan Lu

international memory workshop, (2018)

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Theoretical Analysis of Planar Flat Floating Gate NAND Flash Device and Experimental Study of Floating-Gate (FG) / Charge-Trapping (CT) Fusion Device for Comprehensive Understanding of Charge Storage and Operation Principle

Hang-Ting Lue,Pei-Ying Du,Roger Lo,Chih-Yuan Lu

international memory workshop, pp.1-4, (2016)

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A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance

Roger Lo,Peiying Du,Tzuhsuan Hsu,Chenjun Wu, Jungyi Guo, Chunmin Cheng,Hangting Lue,Yenhao Shih,Tuohung Hou,Kuangyeu Hsieh,Chihyuan Lu

(2015)

Bibtex

A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity

Hang-Ting Lue,Tzu-Hsuan Hsu,Chen-Jun Wu,Wei-Chen Chen,Teng-Hao Yeh,Kuo-Pin Chang,Chih-Chang Hsieh,Pei-Ying Du,Yi-Hsuan Hsiao, Yu-Wei Jiang, Guan-Ru Lee,Roger Lo

international electron devices meeting, (2015): 44-47

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A novel double-trapping BE-SONOS charge-trapping NAND flash device to overcome the erase saturation without using curvature-induced field enhancement effect or high-K (HK)/metal gate (MG) materials

Hangting Lue,Roger Lo,Chihchang Hsieh,Peiying Du,Chihping Chen,Tzuhsuan Hsu,Kuoping Chang,Yenhao Shih,Chihyuan Lu

Electron Devices Meeting, pp.19.6.1-19.6.4, (2014)

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