I work at the intersection of computer architecture, software systems and compilers. My current interests include concurrent systems, specialized accelerator architectures and systems for mobile and web applications, Big Data for program analysis and MOOC tools, and system reliability. Multi-processor Deterministic Replay: I developed several processor-assisted recording solutions for deterministically replaying a parallel program. Since the 1980s, processors have added little to no support for helping programmers improve software reliability. Given the gravity of the parallel programming problem that we were facing, it was high time to change that trend. I was part of a few researchers that started this discussion in the early part of the last decade, and it is gratifying to see industry and academia investing significant effort today to address this challenge. At Michigan, colleagues and I drastically reduced the performance overhead of software multiprocessor replay solutions from over 100x to about ~2% for I/O intensive servers and ~2x for scientific applications. Technology Transfer: In collaboration with Intel, we developed a software replayer named PinPlay using our0020BugNet’s load-value logging solution. Intel used PinPlay for trace-based processor simulation across different platforms and debug commercial workloads. PinPlay integrated with our concurrency testing tool Maple has now been released to public. BugNet’s logging scheme also influenced the implementation of Microsoft’s iDNA replay solution. I worked with Microsoft engineers to use iDNA’s replayer to filter programmer intended data-races and accurately find high priority concurrency bugs. The tool that I helped develop was used to find and fix over 1000 bugs in Windows software. Memory Models: Current Java and C++0x memory models provide weak or no semantics for racy programs, which complicates debugging and could compromise security. Our work disproved the conventional wisdom by showing that an SC-preserving compiler and hardware together costs only about 6% performance overhead. This result could eventually help us guarantee language-level SC. Concurrency Testing Tools: Maple, a concurrency tool for testing untested thread interleavings, and a set of standard concurrency analysis tools (data race detection, systematic testing, probabilistic concurrency testing, etc.) was open-sourced. Also, we published many concurrency bugs that we discovered in our project through an online repository. This infrastructure has been used by researchers from several institutions including Illinois, Washington, Princeton, Microsoft, Google, Tsinghua, and Fudan, to build and evaluate concurrency testing tools. Correctly Executing Unreliable Concurrent Software: Yu and I introduced the idea of thread interleaving memoization. We showed that by remembering tested thread schedules and avoiding untested schedules at runtime, we can tolerate a large fraction of concurrency errors. Colleagues and I also developed an operating system solution that exercised complementary thread schedules during production runs to detect concurrency bugs and avoided them by picking a schedule that is more likely to be correct. Energy Proportional Multi-Core Systems: While some applications (e.g., playing a video) may be dataintensive and demand high bandwidth, several others may not (e.g., text editor). However, today’s homogenous memory and interconnect designs are not energy proportional, as their power consumption does not reduce proportionately while executing applications with a lower data bandwidth demand. We proposed a heterogeneous main memory with mobile and server DRAMs, and a power-gating solution for the on-chip interconnect to help achieve energy proportionality.